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RECEIVER SWITCHING CHARACTERISTICS
0
2
4
6
8
10
0 50 100 150 200
t
pd
− Propagation Delay Time − ns
C
L
− Load Capacitance − pF
t
PLH
t
PHL
TB5T1
SLLS589C – NOVEMBER 2003 – REVISED OCTOBER 2007
over operating free-air temperature range unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 2.5 4
C
L
= 0 pF
(1)
, See Figure 4 and Figure 8 ns
t
PHL
Propagation delay time, high-to-low-level output 2.5 4
t
PLH
Propagation delay time, low-to-high-level output 3 5.5
C
L
= 15 pF, See Figure 4 and Figure 8 ns
t
PHL
Propagation delay time, high-to-low-level output 3 5.5
Propagation delay time,
t
PHZ
6 12 ns
high-level-to-high-impedance output
C
L
= 5 pF, See Figure 5 and Figure 9
Propagation delay time,
t
PLZ
6 12 ns
low-level-to-high-impedance output
Load capacitance (C
L
) = 10 pF, See
0.7 ns
Figure 4 and Figure 8
t
skew1
Pulse width distortion, |t
PHL
- t
PLH
|
Load capacitance (C
L
) = 150 pF, See
4 ns
Figure 4 and Figure 8
C
L
= 10 pF, T
A
= 75 ° C, See Figure 4
0.8 1.4 ns
and Figure 8
Δ t
skew1pp
Part-to-part output waveform skew
(2)
C
L
= 10 pF, T
A
= -40 ° C to 85 ° C, See
1.5 ns
Figure 4 and Figure 8
Δ t
skew
Same part output waveform skew
(2)
C
L
= 10 pF, See Figure 4 and Figure 8 0.3 ns
Propagation delay time,
t
PZH
3 12 ns
high-impedance-to-high-level output
C
L
= 10 pF, See Figure 5 and Figure 8
Propagation delay time,
t
PZL
4 12 ns
high-impedance-to-low-level output
t
TLH
Rise time (20% — 80%) 1 4 ns
C
L
= 10 pF, See Figure 5 and Figure 8
t
THL
Fall time (80% — 20%) 1 4 ns
(1) The propagation delay values with a 0 pF load are based on design and simulation.
(2) Output waveform skews are when devices operate with the same supply voltage, same temperature, have the same packages and the
same test circuits.
NOTE: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total
delay is the sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed
in the table above as the 0 pF load condition. The incremental increase in delay between the 0 pF load condition and
the actual total load capacitance represents the extrinsic, or external delay contributed by the load.
Figure 1. Typical Propagation Delay vs Load Capacitance at 25 ° C
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