Datasheet

TAS5727
www.ti.com SLOS670 –NOVEMBER 2010
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.
Table 15. Channel Interchannel Delay Register Format
BITS DEFINITION D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 – – Minimum absolute delay, 0 DCLK cycles
0 1 1 1 1 1 – – Maximum positive delay, 31 × 4 DCLK cycles
1 0 0 0 0 0 – – Maximum negative delay, –32 × 4 DCLK cycles
0 0 Reserved
SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Delay = (value) × 4 DCLKs
0x11 1 0 1 0 1 1 – – Default value for channel 1
(1)
0x12 0 1 0 1 0 1 – – Default value for channel 2
(1)
0x13 1 0 1 0 1 1 – – Default value for channel 1
(1)
0x14 0 1 0 1 0 1 – – Default value for channel 2
(1)
(1) Default values are in bold.
ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk, etc.) Therefore,
appropriate ICD settings must be used. By default, the device has ICD settings for the AD mode. If used in BD
mode, then update these registers before coming out of all-channel shutdown.
MODE AD MODE BD MODE
0x11 AC B8
0x12 54 60
0x13 AC A0
0x14 54 48
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