Datasheet

23
22
SCLK
32Clks
LRCLK(NoteReversedPhase)
LeftChannel
24-BitMode
1
19 18
20-BitMode
16-BitMode
15
14
MSB LSB
32Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput
2
T0034-01
5
4
9 8
1
0
0
4
5
1
0
23
22 1
19 18
15
14
MSB LSB
5
4
9 8
1
0
0
4
5
1
0
SCLK
TAS5727
www.ti.com SLOS670 –NOVEMBER 2010
SERIAL INTERFACE CONTROL AND TIMING
I
2
S Timing
I
2
S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × f
S
is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
NOTE: All data presented in 2s-complement form with MSB first.
Figure 16. I
2
S 64-f
S
Format
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