Datasheet

TAS5717
TAS5719
www.ti.com SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
DVDD, AVDD, HPVDD –0.3 to 3.6 V
Supply voltage
PVDD_X –0.3 to 30 V
HPL_IN, HPR_IN –0.3 to 4.2 V
3.3-V digital input –0.5 to DVDD + 0.5 V
Input voltage
5-V tolerant
(2)
digital input (except MCLK) –0.5 to DVDD + 2.5
(3)
V
5-V tolerant MCLK input –0.5 to AVDD + 2.5
(3)
V
OUT_x to PGND_x 22
(4)
V
BST_x to PGND_x 32
(4)
V
Input clamp current, I
IK
±20 mA
Output clamp current, I
OK
±20 mA
Operating free-air temperature 0 to 85 °C
Operating junction temperature range 0 to 150 °C
Storage temperature range, T
stg
–40 to 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions are not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
(3) Maximum pin voltage should not exceed 6 V.
(4) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
THERMAL INFORMATION
TAS5717
THERMAL METRIC
(1)
PHP UNIT
48 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
35.2 °C/W
θ
JB
Junction-to-board thermal resistance
(3)
10.9 °C/W
θ
JC(bottom)
Junction-to-case (bottom) thermal resistance
(4)
1.6 °C/W
θ
JC(top)
Junction-to-case (top) thermal resistance
(5)
19.7 °C/W
ψ
JT
Junction-to-top characterization parameter
(6)
3.4 °C/W
ψ
JB
Junction-to-board characterization parameter
(7)
10.1 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
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