Datasheet

TAS5717
TAS5719
SLOS655A –NOVEMBER 2010– REVISED FEBRUARY 2011 www.ti.com
PIN FUNCTIONS (continued)
PIN
5-V
TYPE
(1)
TERMINATION
(2)
DESCRIPTION
TOLERANT
NAME NO.
GVDD_OUT 34 P Gate drive internal regulator output
HPL_IN 1 AI Headphone left IN (single-ended, analog IN)
HPL_OUT 2 AO Headphone left OUT (single-ended, analog OUT)
HP_PWML 48 DO PWM left-channel headphone out
HP_PWMR 47 DO PWM right-channel headphone out
HPR_IN 4 AI Headphone right IN (single-ended, analog IN)
HPR_OUT 3 AO Headphone right OUT (single-ended, analog OUT)
HP_SD 33 AI Headphone shutdown (active-low)
HPVDD 8 P Headphone supply
HPVSS 5 P Headphone ground
LRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample rate clock)
MCLK 15 DI 5-V Pulldown Master clock input
OSC_RES 16 AO Oscillator trim resistor. Connect an 18-kΩ 1% resistor to DVSSO.
OUT_A 44 O Output, half-bridge A
OUT_B 42 O Output, half-bridge B
OUT_C 39 O Output, half-bridge C
OUT_D 37 O Output, half-bridge D
PDN 19 DI 5-V Pullup Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the noise shaper and initiating the PWM
stop sequence.
PGND_AB 43 P Power ground for half-bridges A and B
PGND_CD 38 P Power ground for half-bridges C and D
PLL_FLTM 10 AO PLL negative loop-filter terminal
PLL_FLTP 11 AO PLL positive loop-filter terminal
PVDD_AB 46 P Power-supply input for half-bridge output A
PVDD_CD 35 P Power-supply input for half-bridge output C
RESET 25 DI 5-V Pullup Reset, active-low. A system reset is generated by applying a logic low
to this pin. RESET is an asynchronous control signal that restores the
DAP to its default conditions, and places the PWM in the hard-mute
(high-impedance) state.
SCL 24 DI 5-V I
2
C serial control clock input
SCLK 21 DI 5-V Pulldown Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
SDA 23 DIO 5-V I
2
C serial control data interface input/output
SDIN 22 DI 5-V Pulldown Serial audio data input. SDIN supports three discrete (stereo) data
formats.
SSTIMER 32 AI Controls ramp time of OUT_X to minimize pop. Leave this pin floating
for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The
capacitor determines the ramp time.
STEST 26 DI Factory test pin. Connect directly to DVSS.
VR_ANA 12 P Internally regulated 1.8-V analog supply voltage. This pin must not be
used to power external devices.
VR_DIG 18 P Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
VREG 31 P Digital regulator output. Not to be used for powering external circuitry.
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