Datasheet

CPN
CPP
PLL_FLTP
VR_ANA
HPVDD
AVSS
PLL_FLTM
HPR_IN
HPVSS
HPL_OUT
HPL_IN
RESET
HPR_OUT
STEST
PDN
VR_DIG
OSC_RES
DVSSO
DVDD
MCLK
A_SEL
SCLK
SDIN
LRCLK
AVDD
SDA
SCL
DVSS
GND
VREG
PGND_AB
OUT_A BST_C
OUT_C
GVDD_OUT
HP_SD
HP_PWMR
PVDD_AB OUT_D
BST_D
AGND
HP_PWML BST_A PGND_CD
PVDD_CD
OUT_B
BST_B
SSTIMER
P0075-11
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TAS5717
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TAS5717
TAS5719
www.ti.com SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011
PIN ASSIGNMENT AND DESCRIPTIONS
PIN FUNCTIONS
PIN
5-V
TYPE
(1)
TERMINATION
(2)
DESCRIPTION
TOLERANT
NAME NO.
AGND 30 P Analog ground for power stage
A_SEL 14 DIO This pin is monitored on the rising edge of RESET. A value of 0
makes the I
2
C dev address 0x54, and a value of 1 makes it 0x56.
AVDD 13 P 3.3-V analog power supply
AVSS 9 P Analog 3.3-V supply ground
BST_A 45 P High-side bootstrap supply for half-bridge A
BST_B 41 P High-side bootstrap supply for half-bridge B
BST_C 40 P High-side bootstrap supply for half-bridge C
BST_D 36 P High-side bootstrap supply for half-bridge D
CPN 6 IO Charge-pump flying-capacitor negative connection
CPP 7 IO Charge-pump flying-capacitor positive connection
DVDD 27 P 3.3-V digital power supply
DVSS 28 P Digital ground
DVSSO 17 P Oscillator ground
GND 29 P Analog ground for power stage
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).
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