Datasheet

SCLK
16Clks
LRCLK
LeftChannel
16-BitMode
1 1
15 15
14 14
MSB LSB
16Clks
RightChannel
2-ChannelLeft-JustifiedStereoInput
T0266-02
3 3
2 2
5 5
4 4
9 98 80 0
13 13
10 10
11 1112 12
SCLK
MSB LSB
23
22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
20-BitMode
16-BitMode
15
14
MSB LSB
SCLK
32Clks
RightChannel
2-ChannelRight-Justified(SonyFormat)StereoInput
T0034-03
19 18
1
19 18
1
0
0
0
15
14
15
14
23
22 1
15
14
MSB LSB
19 18
1
19 18
1
0
0
0
15
14
15
14
TAS5717
TAS5719
www.ti.com SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011
NOTE: All data presented in 2s-complement form with MSB first.
Figure 31. Left-Justified 32-f
S
Format
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × f
S
is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks
unused leading data-bit positions.
Figure 32. Right-Justified 64-f
S
Format
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