Datasheet

23
22
SCLK
24Clks
LRCLK
LeftChannel
24-BitMode
1
19 18
20-BitMode
16-BitMode
15
14
MSB LSB
24Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput/Output(24-Bit TransferWordSize)
2
T0092-01
3
2
5
4
9 8
17
16
1
0
0
4
5
13
12
1
09 8
23
22
SCLK
1
19 18
15
14
MSB LSB
3
2
5
4
9 8
17
16
1
0
4
5
13
12
1
09 8
SCLK
16Clks
LRCLK
LeftChannel
16-BitMode
1 1
15 15
14 14
MSB LSB
16Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput
2
T0266-01
3 3
2 2
5 5
4 4
9 98 80
13 13
10 10
11 1112 12
SCLK
MSB LSB
TAS5717
TAS5719
www.ti.com SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011
NOTE: All data presented in 2s-complement form with MSB first.
Figure 27. I
2
S 48-f
S
Format
NOTE: All data presented in 2s-complement form with MSB first.
Figure 28. I
2
S 32-f
S
Format
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × f
S
is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data-bit positions.
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