Datasheet

INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, 0x14, 0x15, 0x16)
OFFSET REGISTER (0x17)
TAS5716
SLOS569 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com
Internal PWM Channels 1, 2, 3, 4, 5, and 6 are mapped into registers 0x11, 0x12 ,0x13, 0x14, 0x15, and 0x16.
Table 14. Channel Interchannel Delay Register Format
BITS DEFINITION D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
Minimum absolute delay, 0 DCLK cycles, default for
0 0 0 0 0 0 0 0
channel 0
(1)
0 1 1 1 1 1 0 0 Maximum positive delay, 31 × 4 DCLK cycles
1 0 0 0 0 0 0 0 Maximum negative delay, – 32 × 4 DCLK cycles
0 0 Unused bits
A
SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Delay = (value) × 4 DCLKs
0x11 0 1 0 0 1 1 0 0 Default value for channel 1
(1)
19
0x12 0 0 1 1 0 1 0 0 Default value for channel 2
(1)
13
0x13 0 0 0 1 1 1 0 0 Default value for channel 3
(1)
7
0x14 0 1 1 0 0 1 0 0 Default value for channel 4
(1)
25
0x15 1 1 0 1 0 0 0 0 Default value for channel 5
(1)
– 12
0x16 1 0 0 1 0 0 0 0 Default value for channel 6
(1)
-28
(1) Default values are in bold.
The offset register is mapped into 0x17.
Table 15. Channel Offset Register Format
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 Minimum absolute offset, 0 DCLK cycles, default for channel 0
(1)
1 1 1 1 1 1 1 1 Maximum absolute offset, 255 DCLK cycles
(1) Default values are in bold.
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