Datasheet

CLOCK CONTROL REGISTER (0x00)
DEVICE ID REGISTER (0x01)
TAS5716
SLOS569 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com
In the manual mode, the clock control register provides a way for the system microprocessor to update the data
and clock rates based on the sample rate and associated clock frequencies. In the auto-detect mode, the clocks
are automatically determined by the TAS5716. In this case, the clock control register contains the auto-detected
clock status as automatically detected (D7 – D2). Bits D7 – D5 select the sample rate. Bits D4 – D2 select the MCLK
frequency. Bit D0 is used in manual mode only. In this mode, when the clocks are updated a 1 must be written to
D0 to inform the DAP that the written clocks are valid.
Table 3. Clock Control Register (0x00)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 – – – – – f
S
= 32-kHz sample rate
0 0 1 – – – – – f
S
= 38-kHz sample rate
0 1 0 – – – – – f
S
= 44.1-kHz sample rate
0 1 1 – – – – – f
S
= 48-kHz sample rate
(1)
1 0 0 – – – – – f
S
= 88.2-kHz sample rate
1 0 1 – – – – – f
S
= 96-kHz sample rate
1 1 0 – – – – – f
S
= 176.4-kHz sample rate
1 1 1 – – – – – f
S
= 192-kHz sample rate
– – – 0 0 0 – – MCLK frequency = 64 × f
S
(2)
– – – 0 0 1 – – MCLK frequency = 128 × f
S
(3)
– – – 0 1 0 – – MCLK frequency = 192 × f
S
– – – 0 1 1 – – MCLK frequency = 256 × f
S
(1)
– – – 1 0 0 – – MCLK frequency = 384 × f
S
(4)
– – – 1 0 1 – – MCLK frequency = 512 × f
S
(4)
– – – 1 1 0 – – Reserved
– – – 1 1 1 – – Reserved
– – – – – – 0 – Bit clock (SCLK) frequency = 64 × f
S
or 32 × f
S
(selected in register 0x04)
(1)
– – – – – – 1 – Bit clock (SCLK) frequency = 48 × f
S
(5)
– – – – – – – 0 Clock not valid (in manual mode only)
(1)
– – – – 1 Clock valid (in manual mode only)
(1) Default values are in bold.
(2) Rate not available for 32-KHz data rate or in AM avoidance mode
(3) Rate not available for 32-kHz data rate
(4) Rate not available for 176.4-kHz and 192-kHz data rates
(5) Rate only available for 192-f
S
and 384-f
S
MCLK frequencies
The device ID register contains the ID code for the firmware revision.
Table 4. General Status Register (0x01)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 – – – – – – – Default
(1)
– 0 1 0 1 0 0 0 Identification code
(1) Default values are in bold.
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