TAS5716 www.ti.com...............................................................................................................................................................................................
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SIMPLIFIED APPLICATION DIAGRAMS Bridge-Tied Load (BTL) Mode 3.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 Single-Ended (SE) 2.1 Mode 3.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Single-Ended (SE) 4.0 Mode 3.
TAS5716 www.ti.com...............................................................................................................................................................................................
Submit Documentation Feedback Product Folder Link(s): TAS5716 Dolby down mix R L 6 sub Sum/ 2 Vol4 ´ ´ Vol3 sc3 sc2 sc1 7 BQ EQ 7 BQ EQ ealpha ealpha BQ 0 Vol2 ´ ´ Vol1 << BQ ealpha ealpha >> NOTES: Nodes identified with red text are turned ON. To write to the input mixers (0x96, 0x99, 0xA9, 0xAA), follow the sequence described on page 40.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 64-PIN, HTQFP PACKAGE PIN FUNCTIONS PIN NAME TYPE NO. (1) 5-V TOLERANT TERMINATION DESCRIPTION (2) AGND 57 P Analog ground for power stage AVCC 58 P Analog power supply for power stage. Connect externally to same potential as PVCC. AVDD 10 P 3.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com PIN FUNCTIONS (continued) PIN NAME TYPE NO.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 PIN FUNCTIONS (continued) PIN NAME TYPE (1) 5-V TOLERANT TERMINATION (2) DESCRIPTION Pullup Reset, active-low. A system reset is generated by applying a logic low to this terminal.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com DISSIPATION RATINGS PACKAGE (1) DERATING FACTOR TA = 25°C POWER RATING TA = 45°C POWER RATING TA = 70°C POWER RATING 10-mm × 10-mm QFP 29 mW/°C 2.89 W 2.31 W 1.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 ELECTRICAL CHARACTERISTICS DC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage 3.3-V TTL and 5-V tolerant (1) IOH = –4 mA VOL Low-level output voltage 3.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com AC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, AVDD, DVDD = 3.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER CL = 30 pF MIN TYP 1.024 MAX UNIT 12.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com I2C SERIAL CONTROL PORT OPERATION Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN No wait states MAX UNIT 400 kHz fSCL Frequency, SCL tw(H) Pulse duration, SCL high 0.
TAS5716 www.ti.com...............................................................................................................................................................................................
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com BACK-END ERROR (BKND_ERR) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER MIN tw(ER) Pulse duration, BKND_ERR active (active-low) tp(valid_high) Programmable. Time to stay in the OUT_x low state.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 HEADPHONE SELECT (HPSEL) PARAMETER tw(MUTE) Pulse duration, HPSEL active td(VOL) Soft volume update time t(SW) Switch-over time (1) MIN MAX 350 None See (1) 0.2 UNIT ns ms 1 ms Defined by rate setting. See the Volume Configuration Register section.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.
TAS5716 www.ti.com...............................................................................................................................................................................................
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.
TAS5716 www.ti.com...............................................................................................................................................................................................
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS, SE CONFIGURATION (continued) EFFICIENCY vs OUTPUT POWER SUPPLY CURRENT vs TOTAL OUTPUT POWER 2.0 100 RL = 4 Ω 90 VCC = 18 V 80 1.5 VCC = 24 V VCC = 18 V ICC − Supply Current − A Efficiency − % 70 60 VCC = 12 V 50 40 30 VCC = 12 V 1.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 DETAILED DESCRIPTION POWER SUPPLY The digital portion of the chip requires 3.3 V, and the power stages can work from 10 V to 26 V. CLOCK, AUTO DETECTION, AND PLL The TAS5716 DAP is a slave device. It accepts MCLK, SCLK, and LRCLK.
Submit Documentation Feedback Product Folder Link(s): TAS5716 SDIN2 SDIN1 SDI 0x04 SDIN1L SDIN1R SDIN2L SDIN2R 6 4 3 2 1 0x20 R' Down Mix 0x21<3:0> L' SUB 2 BQ 7 BQ 7 BQ 0x21<9:8> (L'+R')/2 0x21<11> Bass Management RS LS RF LF 0x21<12> Vol6 0x0D Vol 4 0x0B Vol 3 0x0A Vol 2 0x09 Vol1 0x08 DRC2 drc2_ coeff Drc2_en drc1_ coeff Drc1_en Drc2_dis drc1_ coeff Drc1_en drc1_ coeff Drc1_en DRC1 drc1_ coeff Drc1_en Drc1_dis Noise Shaper AD/BD B T L PWM3 0x13
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 I2S TIMING I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 LEFT-JUSTIFIED Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 RIGHT-JUSTIFIED Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 I2C SERIAL CONTROL INTERFACE The TAS5716 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5716 also supports sequential I2C addressing.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 Single-Byte Read As shown in Figure 42, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a read are actually done.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Dynamic Range Control (DRC) The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/right channels and one DRC for the subwoofer channel. DRC-Compensated Output The DRC input/output diagram is shown in Figure 44.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 Loudness Function The TAS5716 provides a direct form-I biquad for loudness on the subwoofer channel. The first biquad is contained in a gain-compensation circuit that maintains the overall system gain at 1 or less to prevent clipping at loud volume settings.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com b0 x(n) S b1 z a1 –1 z b2 z y(n) Magnitude Truncation –1 a2 –1 z –1 M0012-02 Figure 47. Biquad Filter BANK SWITCHING The TAS5716 uses an approach called bank switching together with automatic sample-rate detection.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 APPLICATION INFORMATION Recovery From Error Protection Mechanisms in the TAS5716 • SCP (short-circuit protection, OCP) protects against shorts across the load, to GND, and to PVCC. • OTP turns off the device if Tdie (typical) > 150°C.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Calculation of Output Signal Level of TAS5716 Feedback Power Stage (Gain Is Independent of PVCC) The gain of the TAS5716 is the total digital gain of the controller multiplied by the gain of the power stage.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 1. 2. 3. 4. 5. 6. 7. Hold ALL logic inputs low. Power up AVDD/DVDD and wait for the inputs to settle in the allowed range. Drive PDN = 1, MUTE = 1, and drive other logic inputs to the desired state.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Writing of Input Mixers Writing of input mixers must follow the guidelines on updating DAP coefficients. The sequence for writing of input mixers, which are internal coefficients, is as follows: 1. Enable input mixer write. Write to register 0xF8: A5 A5 A5 A5 {4 bytes}. 2.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 Table 2. Serial Control Interface Register Summary (continued) SUBADDRESS REGISTER NAME NO.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Table 2. Serial Control Interface Register Summary (continued) SUBADDRESS 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 42 REGISTER NAME ch1_bq[4] ch1_bq[5] ch1_bq[6] ch2_bq[0] ch2_bq[1] ch2_bq[2] ch2_bq[3] ch2_bq[4] ch2_bq[5] NO.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 Table 2. Serial Control Interface Register Summary (continued) SUBADDRESS 0x36 0x37 0x38 REGISTER NAME ch2_bq[6] ch6_bq[0] ch6_bq[1] 0x39 0x3A DRC1 ae NO.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com CLOCK CONTROL REGISTER (0x00) In the manual mode, the clock control register provides a way for the system microprocessor to update the data and clock rates based on the sample rate and associated clock frequencies.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 ERROR STATUS REGISTER (0x02) Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if there are any persistent errors. Table 5.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Table 7.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 SYSTEM CONTROL REGISTER 2 (0x05) Bit D6 is a control bit and bit D5 is a configuration bit. When bit D6 is set low, the system starts playing; otherwise, the outputs are shut down.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com SOFT MUTE REGISTER (0x06) Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle. Default is 0x00. Table 10.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 VOLUME CONFIGURATION REGISTER (0x0E) Bit D7: Reserved = 1 Bit D6: If 0, then biquad 1 (BQ1) volume compensation part only is disabled (default). If 1, then BQ1 volume compensation is enabled.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, 0x14, 0x15, 0x16) Internal PWM Channels 1, 2, 3, 4, 5, and 6 are mapped into registers 0x11, 0x12 ,0x13, 0x14, 0x15, and 0x16. Table 14.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 PWM SHUTDOWN GROUP REGISTER (0x19) Settings of this register determine which PWM channels are active. The default is 0x30 for two BTL output channels and no external subwoofer output.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period when starting up or shutting down channels. The value in this register determines the time for which the PWM inputs switch at 50% duty cycle.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 OSCILLATOR TRIM REGISTER (0x1B) The TAS5716 PWM processor contains an internal oscillator for PLL reference. This reduces system cost because an external reference is not required. Currently, TI recommends a trim resistor value of 18.2 kΩ (1%).
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com INPUT MULTIPLEXER REGISTER (0x20) The hex value for each nibble is the channel number. For each input multiplexer, any input from SDIN1, SDIN2 can be mapped to any internal TAS5716 channel. Table 20.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 Table 20.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com CHANNEL-6 INPUT MULTIPLEXER-2 REGISTER (0x21) Bits D31–D16: Unused Bits D15–D10: Reserved Bits D7–D0: Reserved Table 21.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 AM MODE REGISTER (0x22) See the PurePath Digital™ AM Interference Avoidance application note (SLEA040). Table 22.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.com PWM OUTPUT MUX REGISTER (0x25) This DAP output multiplexer selects which internal PWM channel is output to the external pins. Any channel can be output to any external output pin.
TAS5716 www.ti.com............................................................................................................................................................................................... SLOS569 – JANUARY 2009 Table 25.
TAS5716 SLOS569 – JANUARY 2009............................................................................................................................................................................................... www.ti.
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