Datasheet

SSTIMER
HPL
PLL_FLTP
VR_ANA
PBTL
AVSS
PLL_FLTM
BST_A
HPR
PVDD_A
OUT_A
RESET
PVDD_A
STEST
PDN
VR_DIG
OSC_RES
DVSSO
DVDD
MCLK
A_SEL
SCLK
SDIN
LRCLK
AVDD
SDA
SCL
DVSS
GND
VREG
BST_B
PVDD_B PVDD_C
OUT_C
PVDD_D
BST_D
PGND_AB
OUT_B PGND_CD
OUT_D
AGND
PGND_AB PVDD_B PGND_CD
PVDD_D
BST_C
PVDD_C
GVDD_OUT
P0075-10
PHP Package
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TAS5715
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TAS5715
SLOS645 –AUGUST 2010 www.ti.com
DEVICE INFORMATION
PIN ASSIGNMENT
PIN FUNCTIONS
PIN
5-V
TYPE
(1)
TERMINATION
(2)
DESCRIPTION
TOLERANT
NAME NO.
AGND 30 P Analog ground for power stage
A_SEL 14 DIO This pin is monitored on the rising edge of RESET. A value of 0
makes the I
2
C dev address 0x54 and a value of 1 makes it 0x56.
This pin can be re-used after reset as external HP amplifer shutdown
signal.
AVDD 13 P 3.3-V analog power supply
AVSS 9 P Analog 3.3-V supply ground
BST_A 4 P High-side bootstrap supply for half-bridge A
BST_B 43 P High-side bootstrap supply for half-bridge B
BST_C 42 P High-side bootstrap supply for half-bridge C
BST_D 33 P High-side bootstrap supply for half-bridge D
DVDD 27 P 3.3-V digital power supply
DVSSO 17 P Oscillator ground
DVSS 28 P Digital ground
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).
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