Datasheet

TAS5715
www.ti.com SLOS645 –AUGUST 2010
CLOCK CONTROL REGISTER (0x00)
The clocks and data rates are automatically determined by the TAS5715. The clock control register contains the
auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.
Table 4. Clock Control Register (0x00)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 – – – – – f
S
= 32-kHz sample rate
0 0 1 – – – – – Reserved
(1)
0 1 0 – – – – – Reserved
(1)
0 1 1 – – – – – f
S
= 44.1/48-kHz sample rate
(2)
1 0 0 – – – – – f
S
= 16-kHz sample rate
1 0 1 – – – – – f
S
= 22.05/24 -kHz sample rate
1 1 0 – – – – – f
S
= 8-kHz sample rate
1 1 1 – – – – – f
S
= 11.025/12-kHz sample rate
– – – 0 0 0 – – MCLK frequency = 64 × f
S
(3)
– – – 0 0 1 – – MCLK frequency = 128 × f
S
(3)
– – – 0 1 0 – – MCLK frequency = 192 × f
S
(4)
– – – 0 1 1 – – MCLK frequency = 256 × f
S
(2) (5)
– – – 1 0 0 – – MCLK frequency = 384 × f
S
– – – 1 0 1 – – MCLK frequency = 512 × f
S
– – – 1 1 0 – – Reserved
(1)
– – – 1 1 1 – – Reserved
(1)
– – – – – – 0 – Reserved
(1)
– – – – – – – 0 Reserved
(1)
(1) Reserved registers should not be accessed.
(2) Default values are in bold.
(3) Only available for 44.1-kHz and 48-kHz rates
(4) Rate only available for 32/44.1/48-KHz sample rates
(5) Not available at 8 kHz
DEVICE ID REGISTER (0x01)
The device ID register contains the ID code for the firmware revision.
Table 5. General Status Register (0x01)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 1 0 0 0 0 1 0 Identification code
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