Datasheet

HP/
(SE/ )
SPKR
BTL
VALID
PWM_A(L+)
PWM_C(R+)
PWM_B(L–)
PWM_D(R–)
I C:SCL
SDA
2
HPSD
FAULT(A0/ )
PDN
t
(PDN-HPSD)
Enable
FAULT
HPL/R
HPL/R
t
(exitSDHPamp)
T0453-01
t
(exitSDHP)
t
(HPamp)
=1OutputFAULT
Hi-Z(Ext.Pulldown)
TAS5715
SLOS645 –AUGUST 2010 www.ti.com
Headphone Configuration
• Registers 0x07–0x0B Master/channel headphone volume
• Register 0x19 SDG = 0x30 or 0x00 (PWM3/4 in SDG)
• Registers 0x11–0x12 ICD1/2 = {0xAC, 0x54}
• Register 0x1A<7> Clear bit for headphone mode (HP/SPKR = 0)
• Register 0x1A<4:0> Set to 0 0000 for 0-ms start/stop period
• Register 0x20<23> Clear bit for Ch1 AD mode
• Register 0x20<19> Clear bit for Ch2 AD mode
• Register 0x46<1:0> Clear both bits to disable DRC1 and DRC2
• Register 0x50<7> Set bit to disable EQ
Headphone Mode Power Down
PARAMETE
DESCRIPTION MIN TYP MAX UNIT
R
t
(PDN-HPSD)
Delay from power-down event to headphone amplifier shutdown assertion 2 ms
Exit shutdown wait time before enabling external headphone amp (t
(HPchg)
t
(exitSDHP)
1 + 1.3 × t
(HPchg)
ms
given by register 0x1A<6:5>)
Headphone amp exit shutdown wait time before unmuting (t
(HPamp)
given by 1 + 1.3 ×
t
(exitSDHPamp)
ms
register 0x1C<7:4>) t
(HPamp)
t
(HPamp)
Headphone amp enable/disable wait time (given by register 0x1C<7:4>) t
(HPamp)
ms
Figure 58. Headphone Control Power Down
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