Datasheet

TAS5713
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SLOS637A DECEMBER 2009REVISED AUGUST 2010
Table 4. Serial Control Interface Register Summary (continued)
NO. OF INITIALIZATION
SUBADDRESS REGISTER NAME CONTENTS
BYTES VALUE
0x73 ch1 left_channel_mixer 4 u[31:26], left_mix_1[25:0] 0x0080 0000
0x74 ch2 inline mixer 4 u[31:26], in_mix2[25:0] 0x0080 0000
0x75 inline_DRC_en_mixer_ch2 4 u[31:26], in_mixdrc_2[25:0] 0x0000 0000
0x76 ch2 left_chanel mixer 4 u[31:26], left_mix1[25:0] 0x0000 0000
0x77 ch2 right_channel_mixer 4 u[31:26], right_mix_1[25:0] 0x0080 0000
0x78–0xF7 Reserved
(3)
0xF8 Update dev address key 4 Dev Id Update Key[31:0] (Key = 0xF9A5A5A5) 0x0000 0000
0xF9 Update dev address reg 4 u[31:8],New Dev Id[7:0] (New Dev Id = 0x38 for 0x0000 0036
TAS5713)
0xFA–0xFF 4 Reserved
(3)
0x0000 0000
All DAP coefficients are 3.23 format unless specified otherwise.
Registers 0x3B through 0x46 should be altered only during the initialization phase.
CLOCK CONTROL REGISTER (0x00)
The clocks and data rates are automatically determined by the TAS5713. The clock control register contains the
autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.
Table 5. Clock Control Register (0x00)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 f
S
= 32-kHz sample rate
0 0 1 Reserved
(1)
0 1 0 Reserved
(1)
0 1 1 f
S
= 44.1/48-kHz sample rate
(2)
1 0 0 f
S
= 16-kHz sample rate
1 0 1 f
S
= 22.05/24-kHz sample rate
1 1 0 f
S
= 8-kHz sample rate
1 1 1 f
S
= 11.025/12-kHz sample rate
0 0 0 MCLK frequency = 64 × f
S
(3)
0 0 1 MCLK frequency = 128 × f
S
(3)
0 1 0 MCLK frequency = 192 × f
S
(4)
0 1 1 MCLK frequency = 256 × f
S
(2) (5)
1 0 0 MCLK frequency = 384 × f
S
1 0 1 MCLK frequency = 512 × f
S
1 1 0 Reserved
(1)
1 1 1 Reserved
(1)
0 Reserved
(1)
0 Reserved
(1)
(1) Reserved registers should not be accessed.
(2) Default values are in bold.
(3) Only available for 44.1-kHz and 48-kHz rates
(4) Rate only available for 32/44.1/48-KHz sample rates
(5) Not available at 8 kHz
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