Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Audio amplifier 2-channel (stereo) Class D HTQFP 48 (7x7)

TAS5713

www.ti.com

SLOS637A –DECEMBER 2009–REVISED AUGUST 2010

25-W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC

Check for Samples: TAS5713

FEATURES

• Audio Input/Output – AD and BD PWM-Mode Support

– 25-W Into an 8-Ω Load From a 20-V Supply – Up to 90% Efficient

– Wide PVDD Range, From 8 V to 26 V

• Benefits

– Supports BTL Configuration With 4-Ω Load

– EQ: Speaker Equalization Improves Audio

– Efficient Class-D Operation Eliminates

Performance

Need for Heatsinks

– DRC: Dynamic Range Compression. Can

– One Serial Audio Input (Two Audio

Be Used As Power Limiter. Enables

Channels)

Speaker Protection, Easy Listening,

– I

C Address Selection Pin (Chip Select)

Night-Mode Listening

– Single Output Filter PBTL Support

– Autobank Switching: Preload Coefficients

– Supports 8-kHz to 48-kHz Sample Rate

for Different Sample Rates. No Need to

(LJ/RJ/I

Write New Coefficients to the Part When

• Audio/PWM Processing

Sample Rate Changes

– Independent Channel Volume Controls With

– Autodetect: Automatically Detects

Gain of 24 dB to Mute

Sample-Rate Changes. No Need for

– Programmable Two-Band Dynamic-Range External Microprocessor Intervention

Control

DESCRIPTION

– 22 Programmable Biquads for Speaker EQ

and Other Audio-Processing Features

The TAS5713 is a 25-W, efficient, digital-audio power

amplifier for driving stereo bridge-tied speakers. One

– Programmable Coefficients for DRC Filters

serial data input allows processing of up to two

– DC Blocking Filters

discrete audio channels and seamless integration to

• General Features

most digital audio processors and MPEG decoders.

– I

C Serial Control Interface Operational The device accepts a wide range of input data and

data rates. A fully programmable data path routes

Without MCLK

these channels to the internal speaker drivers.

– Requires Only 3.3 V and PVDD

The TAS5713 is a slave-only device receiving all

– No External Oscillator: Internal Oscillator

clocks from external sources. The TAS5713 operates

for Automatic Rate Detection

with a PWM carrier between a 384-kHz switching rate

– Surface-Mount, 48-Pin, 7-mm × 7-mm

and a 352-KHz switching rate, depending on the input

HTQFP Package

sample rate. Oversampling combined with a

– Thermal and Short-Circuit Protection

fourth-order noise shaper provides a flat noise floor

and excellent dynamic range from 20 Hz to 20 kHz..

– 106-dB SNR, A-Weighted

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (65 pages)

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TAS5713 www.ti.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SIMPLIFIED APPLICATION DIAGRAM 3.
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TAS5713 www.ti.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com FAULT Undervoltage Protection FAULT 4 4 Power On Reset Protection and I/O Logic AGND Temp.
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TAS5713 www.ti.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 PIN FUNCTIONS (continued) PIN NAME NO.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) DVDD, AVDD Supply voltage PVDD_x 3.3-V digital input Input voltage VALUE UNIT –0.3 to 3.6 V –0.3 to 30 V –0.5 to DVDD + 0.5 V 5-V tolerant (2) digital input (except MCLK) –0.5 to DVDD + 2.5 (3) 5-V tolerant MCLK input –0.5 to AVDD + 2.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS PARAMETER TEST CONDITIONS Output sample rate VALUE 11.025/22.05/44.1-kHz data rate ±2% 352.8 48/24/12/8/16/32-kHz data rate ±2% 384 UNIT kHz PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS PARAMETER fMCLKI tr / tf(MCLK) TEST CONDITIONS MIN MCLK frequency 2.8224 MCLK duty cycle 40% TYP 50% Rise/fall time for MCLK LRCLK allowable drift before LRCLK reset MAX UNIT 24.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com AC Characteristics (BTL, PBTL) PVDD_x = 18 V, BTL AD mode, fS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter, fPWM = 384 kHz, TA = 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions (unless otherwise specified).
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER MIN CL = 30 pF TYP 1.024 MAX UNIT 12.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com I2C SERIAL CONTROL PORT OPERATION Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN No wait states MAX UNIT 400 kHz fSCL Frequency, SCL tw(H) Pulse duration, SCL high 0.6 tw(L) Pulse duration, SCL low 1.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 RESET TIMING (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals. PARAMETER tw(RESET) Pulse duration, RESET active td(I2C_ready) Time to enable I2C MIN TYP MAX UNIT 12.0 ms 100 ms RESET tw(RESET) 2 2 I C Active I C Active td(I2C_ready) System Initialization. 2 Enable via I C.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 12V RL = 8Ω T A = 25°C PVDD = 8V RL = 8Ω T A = 25°C PO = 5W 1 1 PO = 2.5W THD+N (%) THD+N (%) PO = 2.5W 0.1 PO = 0.5W 0.1 PO = 1W PO = 1W 0.01 0.01 0.001 20 100 1k Frequency (Hz) 10k 0.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 PVDD = 8V RL = 8Ω T A = 25°C PVDD = 12V RL = 8Ω T A = 25°C 1 1 THD+N (%) THD+N (%) f = 20Hz 0.1 f = 1kHz 0.1 f = 1kHz 0.01 f = 20Hz 0.01 f = 10kHz f = 10kHz 0.001 0.01 0.1 1 Output Power (W) 10 0.001 0.01 40 0.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued) CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY 0 -10 -20 0 PO = 1W PVDD = 18V RL = 8Ω T A = 25°C -10 -20 -30 Crosstalk (dB) Crosstalk (dB) -30 PO = 1W PVDD = 24V RL = 8Ω T A = 25°C -40 -50 -60 -40 -50 -60 Right to Left -70 -70 Right to Left -80 -80 -90 -90 Left to Right Left to Right -100 20 100 1k Frequency (Hz) 10k 20k -100 20 G013 Figure 18.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 4 Ω TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 18V RL = 4Ω T A = 25°C PVDD = 12V RL = 4Ω T A = 25°C PO = 5W 1 1 PO = 5W THD+N (%) THD+N (%) PO = 2.5W 0.1 PO = 1W PO = 1W 0.01 0.001 20 100 0.1 0.01 1k Frequency (Hz) 10k 0.001 20 20k 100 G021 1k Frequency (Hz) 10k 20k G022 Figure 20. Figure 21.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 4 Ω (continued) CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY 0 -10 -10 -20 -30 -30 -40 -40 Crosstalk (dB) Crosstalk (dB) -20 0 PO = 1W PVDD = 12V RL = 4Ω T A = 25°C -50 -60 Right to Left -70 PO = 1W PVDD = 18V RL = 4Ω T A = 25°C -50 -60 Right to Left -70 -80 -80 Left to Right -90 -90 -100 -100 -110 20 100 1k Frequency (Hz) 10k 20k -110 20 G023 Figure 24.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS, PBTL CONFIGURATION, 4 Ω TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 12V RL = 4Ω T A = 25°C PVDD = 24V RL = 4Ω T A = 25°C 1 1 PO = 2.5W PO = 5W THD+N (%) THD+N (%) PO = 5W 0.1 PO = 1W 0.01 0.001 20 100 PO = 2.5W 0.1 0.01 1k Frequency (Hz) 10k PO = 1W 0.001 20 20k 100 G015 1k Frequency (Hz) 20k G016 Figure 26. Figure 27.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION, 4 Ω (continued) OUTPUT POWER vs SUPPLY VOLTAGE EFFICIENCY vs TOTAL OUTPUT POWER 60 100 RL = 4Ω T A = 25°C 90 50 80 PVDD = 24V 70 40 PVDD = 12V Efficiency (%) Output Power (W) THD+N = 10% 30 THD+N = 1% 20 60 50 40 30 20 10 RL = 4Ω T A = 25°C 10 0 0 8 10 12 14 16 18 20 Supply Voltage (V) 22 24 26 0 G019 NOTE: Dashed lines represent thermally limited region. Figure 30.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com DETAILED DESCRIPTION POWER SUPPLY To facilitate system design, the TAS5713 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 speaker load-impedance drops. If the high-current condition situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault condition (i.e., a short circuit on the output) is removed.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com The TAS5713 has robust clock error handling that uses the built-in trimmed oscillator clock to quickly detect changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute) and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the system autodetects the new rate and revert to normal operation.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 2 2-Channel I S (Philips Format) Stereo Input 32 Clks LRCLK (Note Reversed Phase) 32 Clks Right Channel Left Channel SCLK SCLK MSB 24-Bit Mode 23 22 MSB LSB 9 8 5 4 5 4 1 0 1 0 1 0 LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 32.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com 2 2-Channel I S (Philips Format) Stereo Input LRCLK 16 Clks 16 Clks Left Channel Right Channel SCLK SCLK MSB 16-Bit Mode MSB LSB 15 14 13 12 11 10 9 5 8 4 3 2 1 0 LSB 15 14 13 12 11 10 9 5 8 4 3 2 1 T0266-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 34.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 21 LSB 17 16 9 8 5 4 13 12 5 4 1 0 9 1 0 1 0 MSB LSB 21 17 16 9 8 5 4 19 18 17 13 12 5 4 1 0 15 14 13 9 1 0 23 22 1 0 20-Bit Mode 19 18 17 16-Bit Mode 15 14 13 8 8 T0092-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 36.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB-first and is valid on the rising edge of bit clock.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 LSB MSB 23 22 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 20-Bit Mode 16-Bit Mode T0092-03 Figure 39. Right-Justified 48-fS Format Figure 40.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com I2C SERIAL CONTROL INTERFACE The TAS5713 DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations. This is a slave-only device that does not support a multimaster bus environment or wait-state insertion.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress. For example, if a write command is received for a biquad subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the received data is discarded.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com Single-Byte Read As shown in Figure 44, a single-byte data-read transfer begins with the master device transmitting a start condition, followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 Dynamic Range Control (DRC) The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the high-band left/right channels and one DRC for the low-band left/right channels. The DRC input/output diagram is shown in Figure 46.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com BANK SWITCHING The TAS5713 uses an approach called bank switching together with automatic sample-rate detection. All processing features that must be changed for different sample rates are stored internally in three banks. The user can program which sample rates map to each bank. By default, bank 1 is used in the 32-kHz mode, bank 2 is used in the 44.1/48-kHz mode, and bank 3 is used for all other rates.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 48. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number.
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2 Submit Documentation Feedback Product Folder Link(s): TAS5713 PVDD RESET SCL SDA 0 ns 0 ns 100 ms 100 μs 3V 10 ms 8V 6V 13.5 ms Trim 50 ms DAP Config Other Config (1) tPLL has to be greater than 240 ms + 1.3 tstart. This constraint only applies to the first trim command following AVDD/DVDD power-up. It does not apply to trim commands following subsequent resets.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 3V AVDD/DVDD 0 ns 2 ms PDN 0 ns 2 I C 2 ms RESET 2 ms 0 ns 8V PVDD 6V T0420-05 Figure 52. Power Loss Sequence Initialization Sequence Use the following sequence to power-up and initialize the device: 1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V. 2.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com Shutdown Sequence Enter: 1. Write 0x40 to register 0x05. 2. Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A). 3. If desired, reconfigure by returning to step 4 of initialization sequence. 1. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms after trim following AVDD/DVDD powerup ramp). 2. Wait at least 1 ms + 1.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 Table 4. Serial Control Interface Register Summary SUBADDRESS REGISTER NAME NO. OF BYTES INITIALIZATION VALUE CONTENTS A u indicates unused bits.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 40 REGISTER NAME ch1_bq[2] ch1_bq[3] ch1_bq[4] ch1_bq[5] ch1_bq[6] ch2_bq[0] ch2_bq[1] ch2_bq[2] ch2_bq[3] NO.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x34 0x35 0x36 REGISTER NAME ch2_bq[4] ch2_bq[5] ch2_bq[6] 0x36–0x3A 0x3B DRC1 softening filter alpha NO.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F REGISTER NAME ch1 BQ[7] ch1 BQ[8] ch4 BQ[0] ch4 BQ[1] ch2 BQ[7] ch2 BQ[8] ch3 BQ[0] ch3 BQ[1] 0x60–0x61 0x62 NO.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS NO.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com DEVICE ID REGISTER (0x01) The device ID register contains the ID code for the firmware revision. Table 6.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 ERROR STATUS REGISTER (0x02) The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors. Error definitions: • MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing. • SCLK Error: The number of SCLKs per LRCLK is changing. • LRCLK Error: LRCLK frequency is changing.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com SERIAL DATA INTERFACE REGISTER (0x04) As shown in Table 9, the TAS5713 supports nine serial data modes. The default is 24-bit, I2S mode. Table 9.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 SYSTEM CONTROL REGISTER 2 (0x05) When bit D6 is set low, the system exits all-channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute). Table 10.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A) Step size is 0.5 dB. Master volume – 0x07 (default is mute) Channel-1 volume – 0x08 (default is 0 dB) Channel-2 volume – 0x09 (default is 0 dB) Headphone volume – 0x0A (default is 0 dB) Table 12. Master Volume Table 48 HEX dB HEX dB HEX dB HEX dB HEX dB HEX dB 00 24 30 0 60 –24 90 –48 C0 –72 F0 –96 01 23.5 31 –0.5 61 –24.5 91 –48.5 C1 –72.5 F1 –96.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 Table 12. Master Volume Table (continued) HEX dB HEX dB HEX dB HEX dB HEX dB 26 5 56 –19 86 –43 B6 –67 E6 –91 27 4.5 547 –19.5 87 –43.5 B7 –67.5 E7 –91.5 28 4 58 –20 88 –44 B8 –68 E8 –92 29 3.5 59 –20.5 89 –44.5 B9 –68.5 E9 –92.5 2A 3 5A –21 8A –45 BA –69 EA –93 2B 2.5 5B –21.5 8B –45.5 BB –69.5 EB –93.5 2C 2 5C –22 8C –46 BC –70 EC –94 2D 1.5 5D –22.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com MODULATION LIMIT REGISTER (0x10) Table 14. Modulation Limit Register (0x10) D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT 0 0 0 0 0 – – – Reserved – – – – – 0 0 0 99.2% – – – – – 0 0 1 98.4% – – – – – 0 1 0 97.7% – – – – – 0 1 1 96.9% – – – – – 1 0 0 96.1% – – – – – 1 0 1 95.3% – – – – – 1 1 0 94.5% – – – – – 1 1 1 93.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 PWM SHUTDOWN GROUP REGISTER (0x19) Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and 0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the state of bit D5 in the system control register. This register defines which channels belong to the shutdown group (SDG).
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period following an enter/exit all-channel shutdown command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times are only approximate and vary depending on device activity level and I2S clock stability. Table 17.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 OSCILLATOR TRIM REGISTER (0x1B) The TAS5713 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This reduces system cost because an external reference is not required. Currently, TI recommends a reference resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO. Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com INPUT MULTIPLEXER REGISTER (0x20) This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal channels. Table 20.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 CHANNEL 4 SOURCE SELECT REGISTER (0x21) This register selects the channel 4 source. Table 21.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com Table 22.
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TAS5713 www.ti.com SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 BANK SWITCH AND EQ CONTROL (0x50) Table 24. Bank Switching Command D31 D30 D29 D28 D27 D26 D25 D24 0 – – – – – – – 32 kHz, does not use bank 3 (1) 1 – – – – – – – 32 kHz, uses bank 3 – 0 – – – – – – Reserved – – 0 – – – – – Reserved – – – 0 – – – – 44.1/48 kHz, does not use bank 3 (1) – – – 1 – – – – 44.
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TAS5713 SLOS637A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com Table 24. Bank Switching Command (continued) D7 D6 D5 D4 D3 D2 D1 D0 0 EQ ON 1 – – – – – – – EQ OFF (bypass BQ 0–7 of channels 1 and 2) – 0 – – – – – – Reserved (2) – – 0 – – – – – Ignore bank-mapping in bits D31–D8.Use default mapping. (2) – – – 0 – – – – L and R can be written independently.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) TAS5713PHPR ACTIVE Package Type Package Pins Package Drawing Qty HTQFP PHP 48 1000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-3-260C-168 HR (4) 0 to 85 TAS5713 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5713PHPR Package Package Pins Type Drawing HTQFP PHP 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5713PHPR HTQFP PHP 48 1000 336.6 336.6 31.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.