Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
- PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
- ELECTRICAL CHARACTERISTICS
- DC Characteristics
- AC Characteristics (BTL)
- SERIAL AUDIO PORTS SLAVE MODE
- I2C SERIAL CONTROL PORT OPERATION
- RESET TIMING (RESET)
- TYPICAL CHARACTERISTICS, BTL CONFIGURATION
- TYPICAL CHARACTERISTICS, SE CONFIGURATION
- TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
- DETAILED DESCRIPTION
- POWER SUPPLY
- ERROR REPORTING
- DEVICE PROTECTION SYSTEM
- SSTIMER FUNCTIONALITY
- CLOCK, AUTO DETECTION, AND PLL
- SERIAL DATA INTERFACE
- PWM Section
- SERIAL INTERFACE CONTROL AND TIMING
- I2C SERIAL CONTROL INTERFACE
- Output Mode and MUX Selection
- 2.1-Mode Support
- Single-Filter PBTL-Mode Support
- Dynamic Range Control (DRC)
- BANK SWITCHING
- 26-Bit 3.23 Number Format
- Recommended Use Model
- CLOCK CONTROL REGISTER (0x00)
- DEVICE ID REGISTER (0x01)
- ERROR STATUS REGISTER (0x02)
- SYSTEM CONTROL REGISTER 1 (0x03)
- SERIAL DATA INTERFACE REGISTER (0x04)
- SYSTEM CONTROL REGISTER 2 (0x05)
- SOFT MUTE REGISTER (0x06)
- VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A)
- VOLUME CONFIGURATION REGISTER (0x0E)
- MODULATION LIMIT REGISTER (0x10)
- INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
- PWM SHUTDOWN GROUP REGISTER (0x19)
- START/STOP PERIOD REGISTER (0x1A)
- OSCILLATOR TRIM REGISTER (0x1B)
- BKND_ERR REGISTER (0x1C)
- INPUT MULTIPLEXER REGISTER (0x20)
- CHANNEL 4 SOURCE SELECT REGISTER (0x21)
- PWM OUTPUT MUX REGISTER (0x25)
- DRC CONTROL (0x46)
- BANK SWITCH AND EQ CONTROL (0x50)
- Revision History

TAS5711
www.ti.com
SLOS600A –DECEMBER 2009–REVISED AUGUST 2010
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER TEST CONDITIONS VALUE UNIT
11.025/22.05/44.1-kHz data rate ±2% 352.8 kHz
Output sample rate
48/24/12/8/16/32-kHz data rate ±2% 384
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
MCLKI
MCLK Frequency 2.8224 24.576 MHz
MCLK duty cycle 40% 50% 60%
tr /
Rise/fall time for MCLK 5 ns
tf
(MCLK)
LRCLK allowable drift before LRCLK reset 4 MCLKs
External PLL filter capacitor C1 SMD 0603 X7R 47 nF
External PLL filter capacitor C2 SMD 0603 X7R 4.7 nF
External PLL filter resistor R SMD 0603, metal film 470 Ω
ELECTRICAL CHARACTERISTICS
DC Characteristics
TA = 25°, PVCC_x = 18V, DVDD = AVDD = 3.3V, R
L
= 8Ω, BTL AD Mode, FS = 48KHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage A_SEL and SDA I
OH
= –4 mA 2.4 V
DVDD = AVDD = 3 V
V
OL
Low-level output voltage A_SEL and SDA I
OL
= 4 mA 0.5 V
DVDD = AVDD = 3 V
V
I
< V
IL
; DVDD = AVDD 75
I
IL
Low-level input current mA
= 3.6V
V
I
> V
IH
; DVDD = 75
(1)
I
IH
High-level input current mA
AVDD = 3.6V
Normal Mode 48 70
3.3 V supply voltage (DVDD,
I
DD
3.3 V supply current mA
Reset (RESET = low, 24 32
AVDD)
PDN = high)
Normal Mode 30 55
I
PVDD
Half-bridge supply current No load (PVDD_x) mA
Reset (RESET = low, 5 13
PDN = high)
Drain-to-source resistance, LS T
J
= 25°C, includes metallization resistance 180
r
DS(on)
(2)
mΩ
Drain-to-source resistance,
T
J
= 25°C, includes metallization resistance 180
HS
I/O Protection
V
uvp
Undervoltage protection limit PVDD falling 7.2 V
V
uvp,hyst
Undervoltage protection limit PVDD rising 7.6 V
OTE
(3)
Overtemperature error 150 °C
Extra temperature drop
OTE
HYST
(3)
30 °C
required to recover from error
OLPC Overload protection counter f
PWM
= 384 kHz 0.63 ms
I
OC
Overcurrent limit protection Resistor—programmable, max. current, R
OCP
= 22 kΩ 4.5 A
I
OCT
Overcurrent response time 150 ns
OC programming resistor Resistor tolerance = 5% for typical value; the minimum
R
OCP
20 22 kΩ
range resistance should not be less than 20 kΩ.
Internal pulldown resistor at Connected when drivers are tristated to provide bootstrap
R
PD
3 kΩ
the output of each half-bridge capacitor charge.
(1) I
IH
for the PBTL pin has a maximum limit of 200 µA due to an intenal pulldown on the pin.
(2) This does not include bond-wire or pin resistance.
(3) Specified by design
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