Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
- PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
- ELECTRICAL CHARACTERISTICS
- DC Characteristics
- AC Characteristics (BTL)
- SERIAL AUDIO PORTS SLAVE MODE
- I2C SERIAL CONTROL PORT OPERATION
- RESET TIMING (RESET)
- TYPICAL CHARACTERISTICS, BTL CONFIGURATION
- TYPICAL CHARACTERISTICS, SE CONFIGURATION
- TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
- DETAILED DESCRIPTION
- POWER SUPPLY
- ERROR REPORTING
- DEVICE PROTECTION SYSTEM
- SSTIMER FUNCTIONALITY
- CLOCK, AUTO DETECTION, AND PLL
- SERIAL DATA INTERFACE
- PWM Section
- SERIAL INTERFACE CONTROL AND TIMING
- I2C SERIAL CONTROL INTERFACE
- Output Mode and MUX Selection
- 2.1-Mode Support
- Single-Filter PBTL-Mode Support
- Dynamic Range Control (DRC)
- BANK SWITCHING
- 26-Bit 3.23 Number Format
- Recommended Use Model
- CLOCK CONTROL REGISTER (0x00)
- DEVICE ID REGISTER (0x01)
- ERROR STATUS REGISTER (0x02)
- SYSTEM CONTROL REGISTER 1 (0x03)
- SERIAL DATA INTERFACE REGISTER (0x04)
- SYSTEM CONTROL REGISTER 2 (0x05)
- SOFT MUTE REGISTER (0x06)
- VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A)
- VOLUME CONFIGURATION REGISTER (0x0E)
- MODULATION LIMIT REGISTER (0x10)
- INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
- PWM SHUTDOWN GROUP REGISTER (0x19)
- START/STOP PERIOD REGISTER (0x1A)
- OSCILLATOR TRIM REGISTER (0x1B)
- BKND_ERR REGISTER (0x1C)
- INPUT MULTIPLEXER REGISTER (0x20)
- CHANNEL 4 SOURCE SELECT REGISTER (0x21)
- PWM OUTPUT MUX REGISTER (0x25)
- DRC CONTROL (0x46)
- BANK SWITCH AND EQ CONTROL (0x50)
- Revision History
TAS5711
www.ti.com
SLOS600A –DECEMBER 2009–REVISED AUGUST 2010
Table 24. Bank Switching Command (continued)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 EQ ON
1 – – – – – – – EQ OFF (bypass BQ 0-7 of channels 1 and 2)
– 0 – – – – – – Reserved
(2)
– – 0 – – – – – Ignore bank-mapping in bits D31–D8.Use default mapping.
(2)
1 Use bank-mapping in bits D31–D8.
– – – 0 – – – – L and R can be written independently.
(2)
L and R are ganged for EQ biquads; a write to left-channel BQ is also
– – – 1 – – – – written to right-channel BQ. (0x29–0x2F is ganged to 0x30–0x36.Also
0x58–0x5B is ganged to 0x5C–0x5F)
– – – – 0 – – – Reserved
(2)
– – – – – 0 0 0 No bank switching. All updates to DAP
(2)
– – – – – 0 0 1 Configure bank 1 (32 kHz by default)
– – – – – 0 1 0 Configure bank 2 (44.1/48 kHz by default)
– – – – – 0 1 1 Configure bank 3 (other sample rates by default)
– – – – – 1 0 0 Automatic bank selection
– – – – – 1 0 1 Reserved
– – – – – 1 1 X Reserved
(2) Default values are in bold.
SPACER
REVISION HISTORY
Changes from Original (December 2009) to Revision A Page
• Replaced the Dissipations Ratings Table with the Thermal Information Table .................................................................... 8
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