Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
- PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
- ELECTRICAL CHARACTERISTICS
- DC Characteristics
- AC Characteristics (BTL)
- SERIAL AUDIO PORTS SLAVE MODE
- I2C SERIAL CONTROL PORT OPERATION
- RESET TIMING (RESET)
- TYPICAL CHARACTERISTICS, BTL CONFIGURATION
- TYPICAL CHARACTERISTICS, SE CONFIGURATION
- TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
- DETAILED DESCRIPTION
- POWER SUPPLY
- ERROR REPORTING
- DEVICE PROTECTION SYSTEM
- SSTIMER FUNCTIONALITY
- CLOCK, AUTO DETECTION, AND PLL
- SERIAL DATA INTERFACE
- PWM Section
- SERIAL INTERFACE CONTROL AND TIMING
- I2C SERIAL CONTROL INTERFACE
- Output Mode and MUX Selection
- 2.1-Mode Support
- Single-Filter PBTL-Mode Support
- Dynamic Range Control (DRC)
- BANK SWITCHING
- 26-Bit 3.23 Number Format
- Recommended Use Model
- CLOCK CONTROL REGISTER (0x00)
- DEVICE ID REGISTER (0x01)
- ERROR STATUS REGISTER (0x02)
- SYSTEM CONTROL REGISTER 1 (0x03)
- SERIAL DATA INTERFACE REGISTER (0x04)
- SYSTEM CONTROL REGISTER 2 (0x05)
- SOFT MUTE REGISTER (0x06)
- VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A)
- VOLUME CONFIGURATION REGISTER (0x0E)
- MODULATION LIMIT REGISTER (0x10)
- INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
- PWM SHUTDOWN GROUP REGISTER (0x19)
- START/STOP PERIOD REGISTER (0x1A)
- OSCILLATOR TRIM REGISTER (0x1B)
- BKND_ERR REGISTER (0x1C)
- INPUT MULTIPLEXER REGISTER (0x20)
- CHANNEL 4 SOURCE SELECT REGISTER (0x21)
- PWM OUTPUT MUX REGISTER (0x25)
- DRC CONTROL (0x46)
- BANK SWITCH AND EQ CONTROL (0x50)
- Revision History
TAS5711
www.ti.com
SLOS600A –DECEMBER 2009–REVISED AUGUST 2010
Table 22. PWM Output Mux Register (0x25) (continued)
– – 1 0 – – – – Multiplex PWM 3 to OUT_C
– – 1 1 – – – – Multiplex PWM 4 to OUT_C
– – – – 0 0 – – Reserved
(1)
– – – – – – 0 0 Multiplex PWM 1 to OUT_D
– – – – – – 0 1 Multiplex PWM 2 to OUT_D
– – – – – – 1 0 Multiplex PWM 3 to OUT_D
– – – – – – 1 1 Multiplex PWM 4 to OUT_D
(1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 1 0 0 0 1 0 1 Reserved
(1)
DRC CONTROL (0x46)
Each DRC can be enabled independently using the DRC control register. The DRCs are disabled by default.
Table 23. DRC Control Register
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 0 0 0 0 0 0 0 Reserved
(1)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 0 0 0 0 0 0 0 Reserved
(1)
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 0 0 0 0 0 0 0 Reserved
(1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 – – – – – – Reserved
(1)
– – 0 – – – – – Disable complementary (1 - H) low-pass filter generation
– – 1 – – – – – Enable complementary (1 - H) low-pass filter generation
– – – 0 – – – –
– – – 1 – – – –
0 0 Reserved
(1)
– – – – – – 0 – DRC2 turned OFF
(1)
– – – – – – 1 – DRC2 turned ON
– – – – – – – 0 DRC1 turned OFF
(1)
– – – – – – – 1 DRC1 turned ON
(1) Default values are in bold.
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