Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
- PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
- ELECTRICAL CHARACTERISTICS
- DC Characteristics
- AC Characteristics (BTL)
- SERIAL AUDIO PORTS SLAVE MODE
- I2C SERIAL CONTROL PORT OPERATION
- RESET TIMING (RESET)
- TYPICAL CHARACTERISTICS, BTL CONFIGURATION
- TYPICAL CHARACTERISTICS, SE CONFIGURATION
- TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
- DETAILED DESCRIPTION
- POWER SUPPLY
- ERROR REPORTING
- DEVICE PROTECTION SYSTEM
- SSTIMER FUNCTIONALITY
- CLOCK, AUTO DETECTION, AND PLL
- SERIAL DATA INTERFACE
- PWM Section
- SERIAL INTERFACE CONTROL AND TIMING
- I2C SERIAL CONTROL INTERFACE
- Output Mode and MUX Selection
- 2.1-Mode Support
- Single-Filter PBTL-Mode Support
- Dynamic Range Control (DRC)
- BANK SWITCHING
- 26-Bit 3.23 Number Format
- Recommended Use Model
- CLOCK CONTROL REGISTER (0x00)
- DEVICE ID REGISTER (0x01)
- ERROR STATUS REGISTER (0x02)
- SYSTEM CONTROL REGISTER 1 (0x03)
- SERIAL DATA INTERFACE REGISTER (0x04)
- SYSTEM CONTROL REGISTER 2 (0x05)
- SOFT MUTE REGISTER (0x06)
- VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A)
- VOLUME CONFIGURATION REGISTER (0x0E)
- MODULATION LIMIT REGISTER (0x10)
- INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
- PWM SHUTDOWN GROUP REGISTER (0x19)
- START/STOP PERIOD REGISTER (0x1A)
- OSCILLATOR TRIM REGISTER (0x1B)
- BKND_ERR REGISTER (0x1C)
- INPUT MULTIPLEXER REGISTER (0x20)
- CHANNEL 4 SOURCE SELECT REGISTER (0x21)
- PWM OUTPUT MUX REGISTER (0x25)
- DRC CONTROL (0x46)
- BANK SWITCH AND EQ CONTROL (0x50)
- Revision History
TAS5711
SLOS600A –DECEMBER 2009–REVISED AUGUST 2010
www.ti.com
PWM SHUTDOWN GROUP REGISTER (0x19)
Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and
0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the
state of bit D5 in the system control register.
This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group
register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is
set to 0 in system control register 2, 0x05).
Table 16. Shutdown Group Register
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 – – – – – – – Reserved
(1)
– 0 – – – – – – Reserved
(1)
– – 1 – – – – – Reserved
(1)
– – – 1 – – – – Reserved
(1)
– – – – 0 – – – PWM channel 4 does not belong to shutdown group.
(1)
– – – – 1 – – – PWM channel 4 belongs to shutdown group.
– – – – – 0 – – PWM channel 3 does not belong to shutdown group.
(1)
– – – – – 1 – – PWM channel 3 belongs to shutdown group.
– – – – – – 0 – PWM channel 2 does not belong to shutdown group.
(1)
– – – – – – 1 – PWM channel 2 belongs to shutdown group.
– – – – – – – 0 PWM channel 1 does not belong to shutdown group.
(1)
– – – – – – – 1 PWM channel 1 belongs to shutdown group.
(1) Default values are in bold.
52 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5711