Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
- PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
- ELECTRICAL CHARACTERISTICS
- DC Characteristics
- AC Characteristics (BTL)
- SERIAL AUDIO PORTS SLAVE MODE
- I2C SERIAL CONTROL PORT OPERATION
- RESET TIMING (RESET)
- TYPICAL CHARACTERISTICS, BTL CONFIGURATION
- TYPICAL CHARACTERISTICS, SE CONFIGURATION
- TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
- DETAILED DESCRIPTION
- POWER SUPPLY
- ERROR REPORTING
- DEVICE PROTECTION SYSTEM
- SSTIMER FUNCTIONALITY
- CLOCK, AUTO DETECTION, AND PLL
- SERIAL DATA INTERFACE
- PWM Section
- SERIAL INTERFACE CONTROL AND TIMING
- I2C SERIAL CONTROL INTERFACE
- Output Mode and MUX Selection
- 2.1-Mode Support
- Single-Filter PBTL-Mode Support
- Dynamic Range Control (DRC)
- BANK SWITCHING
- 26-Bit 3.23 Number Format
- Recommended Use Model
- CLOCK CONTROL REGISTER (0x00)
- DEVICE ID REGISTER (0x01)
- ERROR STATUS REGISTER (0x02)
- SYSTEM CONTROL REGISTER 1 (0x03)
- SERIAL DATA INTERFACE REGISTER (0x04)
- SYSTEM CONTROL REGISTER 2 (0x05)
- SOFT MUTE REGISTER (0x06)
- VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A)
- VOLUME CONFIGURATION REGISTER (0x0E)
- MODULATION LIMIT REGISTER (0x10)
- INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
- PWM SHUTDOWN GROUP REGISTER (0x19)
- START/STOP PERIOD REGISTER (0x1A)
- OSCILLATOR TRIM REGISTER (0x1B)
- BKND_ERR REGISTER (0x1C)
- INPUT MULTIPLEXER REGISTER (0x20)
- CHANNEL 4 SOURCE SELECT REGISTER (0x21)
- PWM OUTPUT MUX REGISTER (0x25)
- DRC CONTROL (0x46)
- BANK SWITCH AND EQ CONTROL (0x50)
- Revision History

TAS5711
www.ti.com
SLOS600A –DECEMBER 2009–REVISED AUGUST 2010
MODULATION LIMIT REGISTER (0x10)
The modulation limit is the maximum duty cycle of the PWM output waveform.
Table 14. Modulation Limit Register (0x10)
D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT
– – – – – 0 0 0 99.2%
– – – – – 0 0 1 98.4%
– – – – – 0 1 0 97.7%
(1)
– – – – – 0 1 1 96.9%
– – – – – 1 0 0 96.1%
– – – – – 1 0 1 95.3%
– – – – – 1 1 0 94.5%
– – – – – 1 1 1 93.8%
0 0 0 0 0 – – – RESERVED
(1) Default values are in bold.
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
Internal PWM Channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.
Table 15. Channel Interchannel Delay Register Format
BITS DEFINITION D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 – – Minimum absolute delay, 0 DCLK cycles
0 1 1 1 1 1 – – Maximum positive delay, 31 × 4 DCLK cycles
1 0 0 0 0 0 – – Maximum negative delay, –32 × 4 DCLK cycles
0 0 RESERVED
SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Delay = (value) × 4 DCLKs
0x11 1 0 1 0 1 1 – – Default value for channel 1
(1)
0x12 0 1 0 1 0 1 – – Default value for channel 2
(1)
0x13 1 0 1 0 1 1 – – Default value for channel 1
(1)
0x14 0 1 0 1 0 1 – – Default value for channel 2
(1)
(1) Default values are in bold.
ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk etc.). Therefore,
appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD
mode, then update these registers before coming out of all-channel shutdown.
REGISTER AD MODE BD MODE
0x11 AC B8
0x12 54 60
0x13 AC A0
0x14 54 48
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