Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
- PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
- ELECTRICAL CHARACTERISTICS
- DC Characteristics
- AC Characteristics (BTL)
- SERIAL AUDIO PORTS SLAVE MODE
- I2C SERIAL CONTROL PORT OPERATION
- RESET TIMING (RESET)
- TYPICAL CHARACTERISTICS, BTL CONFIGURATION
- TYPICAL CHARACTERISTICS, SE CONFIGURATION
- TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
- DETAILED DESCRIPTION
- POWER SUPPLY
- ERROR REPORTING
- DEVICE PROTECTION SYSTEM
- SSTIMER FUNCTIONALITY
- CLOCK, AUTO DETECTION, AND PLL
- SERIAL DATA INTERFACE
- PWM Section
- SERIAL INTERFACE CONTROL AND TIMING
- I2C SERIAL CONTROL INTERFACE
- Output Mode and MUX Selection
- 2.1-Mode Support
- Single-Filter PBTL-Mode Support
- Dynamic Range Control (DRC)
- BANK SWITCHING
- 26-Bit 3.23 Number Format
- Recommended Use Model
- CLOCK CONTROL REGISTER (0x00)
- DEVICE ID REGISTER (0x01)
- ERROR STATUS REGISTER (0x02)
- SYSTEM CONTROL REGISTER 1 (0x03)
- SERIAL DATA INTERFACE REGISTER (0x04)
- SYSTEM CONTROL REGISTER 2 (0x05)
- SOFT MUTE REGISTER (0x06)
- VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A)
- VOLUME CONFIGURATION REGISTER (0x0E)
- MODULATION LIMIT REGISTER (0x10)
- INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
- PWM SHUTDOWN GROUP REGISTER (0x19)
- START/STOP PERIOD REGISTER (0x1A)
- OSCILLATOR TRIM REGISTER (0x1B)
- BKND_ERR REGISTER (0x1C)
- INPUT MULTIPLEXER REGISTER (0x20)
- CHANNEL 4 SOURCE SELECT REGISTER (0x21)
- PWM OUTPUT MUX REGISTER (0x25)
- DRC CONTROL (0x46)
- BANK SWITCH AND EQ CONTROL (0x50)
- Revision History
+
L
R
+
+
+
+
+
Vol1
Vol2
ealpha
1BQ
1BQ
1BQ
1BQ
6BQ
6BQ
1BQ
1BQ
1BQ
Input Muxing
Log
Math
Attack
Decay
1
Master ON/OFF
(0x46[0])
Energy
MAXMUX
ealpha
B0321-08
1
1
1
1
1
1
51 V1OM
52 V2OM
I2C:57
VDISTB
I2C:56
VDISTA
60 V6OM
55
2A
I2C:53 – V1IM
31
2B–2F, 58
32–36, 5C
59
I C Subaddress in Red
2
5D
5E
29
30
I2C:54 – V2IM
L
R
1BQ
1BQ
Vol1
5A
5B
21 (D8, D9)
½
½
61
+
+
+
–1
0
Auto-lp
(0x46 Bit 5)
Log
Math
Attack
Decay
1
Master ON/OFF
(0x46[1])
Energy
MAXMUX
ealpha
ealpha
ealpha
Vol2
+
+
3D
3D
3A
3A
TAS5711
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SLOS600A –DECEMBER 2009–REVISED AUGUST 2010
DAP Process Structure
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