Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
- PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
- ELECTRICAL CHARACTERISTICS
- DC Characteristics
- AC Characteristics (BTL)
- SERIAL AUDIO PORTS SLAVE MODE
- I2C SERIAL CONTROL PORT OPERATION
- RESET TIMING (RESET)
- TYPICAL CHARACTERISTICS, BTL CONFIGURATION
- TYPICAL CHARACTERISTICS, SE CONFIGURATION
- TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
- DETAILED DESCRIPTION
- POWER SUPPLY
- ERROR REPORTING
- DEVICE PROTECTION SYSTEM
- SSTIMER FUNCTIONALITY
- CLOCK, AUTO DETECTION, AND PLL
- SERIAL DATA INTERFACE
- PWM Section
- SERIAL INTERFACE CONTROL AND TIMING
- I2C SERIAL CONTROL INTERFACE
- Output Mode and MUX Selection
- 2.1-Mode Support
- Single-Filter PBTL-Mode Support
- Dynamic Range Control (DRC)
- BANK SWITCHING
- 26-Bit 3.23 Number Format
- Recommended Use Model
- CLOCK CONTROL REGISTER (0x00)
- DEVICE ID REGISTER (0x01)
- ERROR STATUS REGISTER (0x02)
- SYSTEM CONTROL REGISTER 1 (0x03)
- SERIAL DATA INTERFACE REGISTER (0x04)
- SYSTEM CONTROL REGISTER 2 (0x05)
- SOFT MUTE REGISTER (0x06)
- VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A)
- VOLUME CONFIGURATION REGISTER (0x0E)
- MODULATION LIMIT REGISTER (0x10)
- INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
- PWM SHUTDOWN GROUP REGISTER (0x19)
- START/STOP PERIOD REGISTER (0x1A)
- OSCILLATOR TRIM REGISTER (0x1B)
- BKND_ERR REGISTER (0x1C)
- INPUT MULTIPLEXER REGISTER (0x20)
- CHANNEL 4 SOURCE SELECT REGISTER (0x21)
- PWM OUTPUT MUX REGISTER (0x25)
- DRC CONTROL (0x46)
- BANK SWITCH AND EQ CONTROL (0x50)
- Revision History
TAS5711
www.ti.com
SLOS600A –DECEMBER 2009–REVISED AUGUST 2010
SYSTEM CONTROL REGISTER 2 (0x05)
When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs
are shut down(hard mute).
Table 10. System Control Register 2 (0x05)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 – – – – – – – Mid-Z ramp disabled
(1)
1 – – – – – – – Mid-Z ramp enabled
– 0 – – – – – – Exit all-channel shutdown (normal operation)
– 1 – – – – – – Enter all-channel shutdown (hard mute)
(1)
– – – – 0 – – – Subchannel in AD mode
– – – – 1 – – – Subchannel in BD mode
– – – – – 0 – – 2.0 mode [2.0 BTL]
(1)
– – – – – 1 – – 2.1 mode [2 SE + 1 BTL]
– 0 – – – – – – Exit all-channel shutdown (normal operation)
– – – – – – 0 – A_SEL configured as input
(1)
– – – – – – 1 – A_SEL configured as FAULT output
– – 0 0 – – – 0 Reserved
(1)
(1) Default values are in bold.
SOFT MUTE REGISTER (0x06)
Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).
Table 11. Soft Mute Register (0x06)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 – – – Reserved
(1)
– – – – – 0 – – Soft unmute channel 3
(1)
– – – – – 1 – – Soft mute channel 3
– – – – – – 0 – Soft unmute channel 2
(1)
– – – – – – 1 – Soft mute channel 2
– – – – – – – 0 Soft unmute channel 1
(1)
– – – – – – – 1 Soft mute channel 1
(1) Default values are in bold.
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