Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
- PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
- ELECTRICAL CHARACTERISTICS
- DC Characteristics
- AC Characteristics (BTL)
- SERIAL AUDIO PORTS SLAVE MODE
- I2C SERIAL CONTROL PORT OPERATION
- RESET TIMING (RESET)
- TYPICAL CHARACTERISTICS, BTL CONFIGURATION
- TYPICAL CHARACTERISTICS, SE CONFIGURATION
- TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
- DETAILED DESCRIPTION
- POWER SUPPLY
- ERROR REPORTING
- DEVICE PROTECTION SYSTEM
- SSTIMER FUNCTIONALITY
- CLOCK, AUTO DETECTION, AND PLL
- SERIAL DATA INTERFACE
- PWM Section
- SERIAL INTERFACE CONTROL AND TIMING
- I2C SERIAL CONTROL INTERFACE
- Output Mode and MUX Selection
- 2.1-Mode Support
- Single-Filter PBTL-Mode Support
- Dynamic Range Control (DRC)
- BANK SWITCHING
- 26-Bit 3.23 Number Format
- Recommended Use Model
- CLOCK CONTROL REGISTER (0x00)
- DEVICE ID REGISTER (0x01)
- ERROR STATUS REGISTER (0x02)
- SYSTEM CONTROL REGISTER 1 (0x03)
- SERIAL DATA INTERFACE REGISTER (0x04)
- SYSTEM CONTROL REGISTER 2 (0x05)
- SOFT MUTE REGISTER (0x06)
- VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A)
- VOLUME CONFIGURATION REGISTER (0x0E)
- MODULATION LIMIT REGISTER (0x10)
- INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
- PWM SHUTDOWN GROUP REGISTER (0x19)
- START/STOP PERIOD REGISTER (0x1A)
- OSCILLATOR TRIM REGISTER (0x1B)
- BKND_ERR REGISTER (0x1C)
- INPUT MULTIPLEXER REGISTER (0x20)
- CHANNEL 4 SOURCE SELECT REGISTER (0x21)
- PWM OUTPUT MUX REGISTER (0x25)
- DRC CONTROL (0x46)
- BANK SWITCH AND EQ CONTROL (0x50)
- Revision History

2 sm
2 sm
AVDD/DVDD
PDN
PVDD
RESET
T0420-05
3V
8V
6V
I C
2
2ms
0ns
0ns
0ns
TAS5711
www.ti.com
SLOS600A –DECEMBER 2009–REVISED AUGUST 2010
Figure 58. Power Loss Sequence
Recommended Command Sequences
Initialization Sequence
Use the following sequence to power-up and initialize the device:
1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V.
2. Initialize digital inputs and PVDD supply as follows:
• Drive RESET = 0, PDN = 1, and other digital inputs to their desired state while ensuring that
all are never more than 2.5 V above AVDD/DVDD. Wait at least 100 µs, drive RESET = 1,
and wait at least another 13.5 ms.
• Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs
after AVDD/DVDD reaches 3 V. Then wait at least another 10 µs.
3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms.
4. Configure the DAP via I
2
C (see Users's Guide for typical values).
5. Configure remaining registers.
6. Exit shutdown (sequence defined below).
Normal Operation
The following are the only events supported during normal operation:
1. Writes to master/channel volume registers.
2. Writes to soft mute register.
3. Enter and exit shutdown (sequence defined below).
Note: Event 3 is not supported for 240 ms + 1.3 × t
start
after trim following AVDD/DVDD powerup ramp
(where t
start
is 300 ms when mid-Z ramp is enabled and is otherwise specified by register 0x1A).
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