Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
- PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
- ELECTRICAL CHARACTERISTICS
- DC Characteristics
- AC Characteristics (BTL)
- SERIAL AUDIO PORTS SLAVE MODE
- I2C SERIAL CONTROL PORT OPERATION
- RESET TIMING (RESET)
- TYPICAL CHARACTERISTICS, BTL CONFIGURATION
- TYPICAL CHARACTERISTICS, SE CONFIGURATION
- TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
- DETAILED DESCRIPTION
- POWER SUPPLY
- ERROR REPORTING
- DEVICE PROTECTION SYSTEM
- SSTIMER FUNCTIONALITY
- CLOCK, AUTO DETECTION, AND PLL
- SERIAL DATA INTERFACE
- PWM Section
- SERIAL INTERFACE CONTROL AND TIMING
- I2C SERIAL CONTROL INTERFACE
- Output Mode and MUX Selection
- 2.1-Mode Support
- Single-Filter PBTL-Mode Support
- Dynamic Range Control (DRC)
- BANK SWITCHING
- 26-Bit 3.23 Number Format
- Recommended Use Model
- CLOCK CONTROL REGISTER (0x00)
- DEVICE ID REGISTER (0x01)
- ERROR STATUS REGISTER (0x02)
- SYSTEM CONTROL REGISTER 1 (0x03)
- SERIAL DATA INTERFACE REGISTER (0x04)
- SYSTEM CONTROL REGISTER 2 (0x05)
- SOFT MUTE REGISTER (0x06)
- VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A)
- VOLUME CONFIGURATION REGISTER (0x0E)
- MODULATION LIMIT REGISTER (0x10)
- INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
- PWM SHUTDOWN GROUP REGISTER (0x19)
- START/STOP PERIOD REGISTER (0x1A)
- OSCILLATOR TRIM REGISTER (0x1B)
- BKND_ERR REGISTER (0x1C)
- INPUT MULTIPLEXER REGISTER (0x20)
- CHANNEL 4 SOURCE SELECT REGISTER (0x21)
- PWM OUTPUT MUX REGISTER (0x25)
- DRC CONTROL (0x46)
- BANK SWITCH AND EQ CONTROL (0x50)
- Revision History
CH1_audio
CH1_audio
CH1_audio
CH1_audio
CH2_audio
CH2_audio
CH3_audio
CH3_audio
CH2_audio
CH2_audio
PWM1
PWM1
PWM1
PWM1
PWM2
PWM2
PWM2
PWM2
PWM3
PWM3
PWM3
PWM3
PWM4
PWM4
PWM4
PWM4
2.0 BTL AD
0x20 (23) = 0
0x20 (19) = 0
0x05 (3) = X
0x05 (2) = 0
Reg setting
2.0 BTL BD
0x20 (23) = 1
0x20 (19) = 1
0x05 (3) = X
0x05 (2) = 0
Reg setting
2.1 SE, BTL-AD
0x20 (23) = 0
0x20 (19) = 0
0x05 (3) = 0
0x05 (2) = 1
Reg setting
2.1 SE, BTL-BD
0x20 (23) = 0
0x20 (19) = 0
0x05 (3) = 1
0x05 (2) = 1
Reg setting
A
A
A
A
B
B
B
B
C
C
C
C
D
D
D
D
B0378-01
TAS5711
SLOS600A –DECEMBER 2009–REVISED AUGUST 2010
www.ti.com
Output Mode and MUX Selection
Figure 51. Output Mode and MUX Selection
2.1-Mode Support
The TAS5711 uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode
operation.To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05 bit
D2 must be set to 1. The SSTIMER pin should be left floating in this mode.
Single-Filter PBTL-Mode Support
The TAS5711 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected before
the LC filter. In order to put the part in PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the
turnoff of half-bridges A and B (and similarly C/D) if an overcurrent condition is detected in either half-bridge.
There is a pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating.
PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should
be written with a value of 0x01 10 32 45. Also, the PWM shutdown register (0x19) should be written with a value
of 0x3A.
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