Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- THERMAL INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
- PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
- ELECTRICAL CHARACTERISTICS
- DC Characteristics
- AC Characteristics (BTL)
- SERIAL AUDIO PORTS SLAVE MODE
- I2C SERIAL CONTROL PORT OPERATION
- RESET TIMING (RESET)
- TYPICAL CHARACTERISTICS, BTL CONFIGURATION
- TYPICAL CHARACTERISTICS, SE CONFIGURATION
- TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
- DETAILED DESCRIPTION
- POWER SUPPLY
- ERROR REPORTING
- DEVICE PROTECTION SYSTEM
- SSTIMER FUNCTIONALITY
- CLOCK, AUTO DETECTION, AND PLL
- SERIAL DATA INTERFACE
- PWM Section
- SERIAL INTERFACE CONTROL AND TIMING
- I2C SERIAL CONTROL INTERFACE
- Output Mode and MUX Selection
- 2.1-Mode Support
- Single-Filter PBTL-Mode Support
- Dynamic Range Control (DRC)
- BANK SWITCHING
- 26-Bit 3.23 Number Format
- Recommended Use Model
- CLOCK CONTROL REGISTER (0x00)
- DEVICE ID REGISTER (0x01)
- ERROR STATUS REGISTER (0x02)
- SYSTEM CONTROL REGISTER 1 (0x03)
- SERIAL DATA INTERFACE REGISTER (0x04)
- SYSTEM CONTROL REGISTER 2 (0x05)
- SOFT MUTE REGISTER (0x06)
- VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A)
- VOLUME CONFIGURATION REGISTER (0x0E)
- MODULATION LIMIT REGISTER (0x10)
- INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
- PWM SHUTDOWN GROUP REGISTER (0x19)
- START/STOP PERIOD REGISTER (0x1A)
- OSCILLATOR TRIM REGISTER (0x1B)
- BKND_ERR REGISTER (0x1C)
- INPUT MULTIPLEXER REGISTER (0x20)
- CHANNEL 4 SOURCE SELECT REGISTER (0x21)
- PWM OUTPUT MUX REGISTER (0x25)
- DRC CONTROL (0x46)
- BANK SWITCH AND EQ CONTROL (0x50)
- Revision History
SCL
SDA
t
w(H)
t
w(L)
t
r
t
f
t
su1
t
h1
T0027-01
SCL
SDA
t
h2
t
(buf)
t
su2
t
su3
Start
Condition
Stop
Condition
T0028-01
TAS5711
SLOS600A –DECEMBER 2009–REVISED AUGUST 2010
www.ti.com
I
2
C SERIAL CONTROL PORT OPERATION
Timing characteristics for I
2
C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
f
SCL
Frequency, SCL No wait states 400 kHz
t
w(H)
Pulse duration, SCL high 0.6 ms
t
w(L)
Pulse duration, SCL low 1.3 ms
t
r
Rise time, SCL and SDA 300 ns
t
f
Fall time, SCL and SDA 300 ns
t
su1
Setup time, SDA to SCL 100 ns
t
h1
Hold time, SCL to SDA 0 ns
t
(buf)
Bus free time between stop and start condition 1.3 ms
t
su2
Setup time, SCL to start condition 0.6 ms
t
h2
Hold time, start condition to SCL 0.6 ms
t
su3
Setup time, SCL to stop condition 0.6 ms
C
L
Load capacitance for each bus line 400 pF
Figure 3. SCL and SDA Timing
Figure 4. Start and Stop Conditions Timing
12 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TAS5711