Datasheet

PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
ELECTRICAL CHARACTERISTICS
TAS5710
SLOS605 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
MCLKI
MCLK Frequency 2.8224 24.576 MHz
MCLK duty cycle 40% 50% 60%
tr /
Rise/fall time for MCLK 5 ns
tf
(MCLK)
LRCLK allowable drift before LRCLK reset 4 MCLKs
External PLL filter capacitor C1 SMD 0603 Y5V 47 nF
External PLL filter capacitor C2 SMD 0603 Y5V 4.7 nF
External PLL filter resistor R SMD 0603, metal film 470 Ω
DC Characteristics, BD BTL Mode, F
S
= 48 kHz, T
A
= 25 ° C, PVCC_X = AVCC = 18 V, DVDD=AVDD= 3.3V, R
L
= 8 Ω (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage FAULT and SDA I
OH
= – 4 mA , 2.4 V
DVDD=AVDD=3.0 V
V
OL
Low-level output voltage FAULT and SDA I
OL
= 4 mA , 0.5 V
DVDD=AVDD=3.0 V
|VOS| Class-D output offset voltage 26 mV
V
BYPASS
PVCC/8 reference for analog section No load 2.1 2.26 2.4 V
Digital Inputs V
I
≤ V
IL
75
I
IL
Low-level input current µ A
DVDD = AVDD = 3.6 V
Digital Inputs V
I
≥ V
IH
75
I
IH
High-level input current µ A
DVDD = AVDD = 3.6 V
Normal mode 43 77
3.3V Supply voltage (DVDD +
I
DD
3.3-V supply current mA
Reset ( RESET = low, PDN 19 24
AVDD)
= high)
Normal Mode 34 60 mA
I
CC
Half-Bridge supply current No Load (PVCC + AVCC)
Reset ( RESET = low, PDN 54 310
µ A
= high)
Drain-to-source resistance, high-side V
CC
= 18 V , I
O
= 500 mA, 240
r
DS(on)
(1)
T
J
= 25 ° C, includes m Ω
240
Drain-to-source resistance, low-side
metalization resistance
Protection
Undervoltage protection 8.4
V
uvp
PVCC_X = AVCC falling V
limit
Undervoltage protection 8.5
V
uvp,hyst
PVCC_X = AVCC rising V
limit
Overvoltage protection 27.5
V
ovp
PVCC_X = AVCC rising V
limit
Overvoltage protection 27.2
V
ovp,hyst
PVCC_X = AVCC falling V
limit
OTE
(2)
Over temperature error (output shutdown, unlatched) 150 ° C
OTE
HYST
(2)
Extra temperature drop required to recover from error 15 ° C
(1) This does not include bond-wire or pin resistance.
(2) Specified by design
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