Datasheet

TAS5710
SLOS605 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com
PIN FUNCTIONS (continued)
PIN
TYPE 5-V TERMINATION
DESCRIPTION
(1)
TOLERANT
(2)
NAME NO.
LRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample rate clock)
MCLK 15 DI 5-V Pulldown Master Clock Input
OSC_RES 16 AO Oscillator trim resistor. Connect an 18.2-k Ω 1% resistor to DVSSO.
OUT_A 4 O Output, half-bridge A
OUT_B 1 O Output, half-bridge B
OUT_C 36 O Output, half-bridge C
OUT_D 33 O Output, half-bridge D
PDN 19 DI 5-V Pullup Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the Noise Shaper and initiating PWM stop
sequence.
PGND_A 5, 6 P Power ground for half-bridge A
PGND_B 2, 3 P Power ground for half-bridge B
PGND_C 34, 35 P Power ground for half-bridge C
PGND_D 31, 32 P Power ground for half-bridge D
PLL_FLTM 10 AO PLL negative loop filter terminal
PLL_FLTP 11 AO PLL positive loop filter terminal
PVCC_A 7, 8 P Power supply input for half-bridge output A
PVCC_B 48 P Power supply input for half-bridge output B
PVCC_C 37 P Power supply input for half-bridge output C
PVCC_D 29, 30 P Power supply input for half-bridge output D
RESET 25 DI 5-V Pullup Reset, active-low. A system reset is generated by applying a logic low
to this pin. RESET is an asynchronous control signal that restores the
DAP to its default conditions, and places the PWM in the hard mute
state (3-stated).
SCL 24 DI 5-V I
2
C serial control clock input
SCLK 21 DI 5-V Pulldown Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
SDA 23 DIO 5-V I
2
C serial control data interface input/output
SDIN 22 DI 5-V Pulldown Serial audio data input. SDIN supports three discrete (stereo) data
formats.
STEST 26 DI Factory test pin. Connect directly to DVSS.
FAULT 14 DO Backend error indicator. Asserted LOW for over current errors.
De-asserted upon recovery from error condition.
VR_ANA 12 P Internally regulated 1.8-V analog supply voltage. This pin must not be
used to power external devices.
VR_DIG 18 P Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
VCLAMP_AB 46 AO Internally generated voltage supply for channel A and B gate drive.
This pin must not be used to power external devices. Connect only to
external decoupling capacitor
VCLAMP_CD 39 AO Internally generated voltage supply for channel C and D gate drive.
This pin must not be used to power external devices. Connect only to
external decoupling capacitor
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