Datasheet

ERROR STATUS REGISTER (0x02)
SYSTEM CONTROL REGISTER 1 (0x03)
TAS5710
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............................................................................................................................................................................................... SLOS605 JANUARY 2009
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error Definitions:
MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
SCLK Error: The number of SCLKs per LRCLK is changing.
LRCLK Error: LRCLK frequency is changing.
Frame Slip: LRCLK phase is drifting with respect to internal Frame Sync.
Table 5. Error Status Register (0x02)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 - MCLK error
1 PLL autolock error
1 SCLK error
1 LRCLK error
1 Frame slip
1 Over current error
0 0 0 0 0 0 0 - No errors
(1)
(1) Default values are in bold.
The system control register 1 has several functions:
Bit D7: If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter ( 3 dB cutoff < 1 Hz) for each channel is enabled (default).
Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes same
time as volume ramp defined in reg 0X0E.
If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step
volume ramp
Bits D1 D0: Select de-emphasis
Table 6. System Control Register 1 (0x03)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 PWM high-pass (dc blocking) disabled
1 PWM high-pass (dc blocking) enabled
(1)
0 Reserved
(1)
0 Soft unmute on recovery from clock error
1 Hard unmute on recovery from clock error
(1)
0 Reserved
(1)
0 Reserved
(1)
0 Reserved
(1)
0 0 No de-emphasis
(1)
0 1 Reserved
1 0 De-emphasis for f
S
= 44.1 kHz
1 1 De-emphasis for f
S
= 48 kHz
(1) Default values are in bold.
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