Datasheet

TAS5710
SLOS605 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com
Shutdown Sequence
Enter:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
2. Write 0x40 to register 0x05.
3. Wait at least 1ms+1.3 × t
stop
(where t
stop
is specified by register 0x1A).
4. Once in shutdown, stable clocks are not required while device remains idle.
5. If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before
returning to step 4 of initialization sequence.
Exit:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
2. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms
after trim following AVDD/DVDD powerup ramp).
3. Wait at least 1ms+1.3 × t
start
(where t
start
is specified by register 0x1A).
4. Proceed with normal operation.
Controlled Powerdown Sequence
Use the following sequence to powerdown the device and its supplies when time permits a controlled
shutdown:
1. Enter shutdown (sequence defined above).
2. Assert RESET=0.
3. Drive digital inputs low and ramp down PVCC/AVCC supply as follows:
• Drive all digital inputs low after RESET has been low for at least 2us.
• Ramp down PVCC/AVCC while ensuring that it remains above 10V until RESET has been low
for at least 2 µ s.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVCC/AVCC is below 7.5V
and observing absolute maximum ratings for digital inputs.
Power Loss Sequence (BD BTL)
Use the following sequence to powerdown a BD BTL device and its supplies in case of sudden power loss
when time does not permit a controlled shutdown:
1. Assert PDN = 0 and wait at least 2ms.
2. Assert HIZ = 0.
3. Drive digital inputs low and ramp down PVCC/AVCC supply as follows:
• Drive all digital inputs low after HIZ has been low for at least 4 µ s.
• Ramp down PVCC/AVCC while ensuring that it remains above 10V until HIZ has been low for at
least 4 µ s.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVCC/AVCC is below 7.5V
and observing absolute maximum ratings for digital inputs.
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