TAS5710 www.ti.com...............................................................................................................................................................................................
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SIMPLIFIED APPLICATION DIAGRAM 3.
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R L Submit Documentation Feedback Product Folder Link(s): TAS5710 R L 30 1BQ 29 1BQ Sum/2 [2] [3] [2] [3] + + 54 31 1BQ 2A 1BQ 53 [0] [1] [0] [1] + + 32-36 5BQ 50 [D7] 2B-2F 5BQ 55 21 [D8] [0] [1] [2] + 5A-5B 2BQ 5E-5F 2BQ 5C-5D 2BQ 58-59 2BQ 2 Vol1 Vol2 Vol1 3D ealpha 3D ealpha 3A ealpha 3A ealpha Log Math Log Math Energy MAXMUX 4 Energy MAXMUX Hex numbers refer to I C subaddresses [i] = byte "i" of multibyte subaddress [Di] = bit "i" of subadd
TAS5710 www.ti.com...............................................................................................................................................................................................
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com PIN FUNCTIONS (continued) PIN NAME NO.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply voltage Input voltage (1) (2) VALUE UNIT DVDD, AVDD –0.3 to 3.6 V PVCC_X, AVCC –0.3 to 30 V 3.3-V digital inputs (except HIZ) –0.5 to DVDD + 0.5 V 3.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS PARAMETER fMCLKI tr / tf(MCLK) TEST CONDITIONS MIN MCLK Frequency 2.8224 MCLK duty cycle 40% TYP 50% MAX UNIT 24.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 AC Characteristics PVCC_x = AVCC = 18V, BTL BD Mode, FS=48KHz, TA = 25°C, AVDD = DVDD = 3.3 V, RL = 8 Ω, CBST = 220 nF, Audio Frequency = 1 kHz, AES17 filter (unless otherwise noted).
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER MIN CL = 30 pF TYP 1.024 MAX UNIT 12.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 I2C SERIAL CONTROL PORT OPERATION Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN No wait states MAX UNIT 400 kHz fSCL Frequency, SCL tw(H) Pulse duration, SCL high 0.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com RESET TIMING (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals.
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TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) CROSSTALK vs FREQUENCY −40 −50 PO = 1 W PVCC = 24 V RL = 8 Ω Crosstalk − dB −60 Left to Right −70 Right to Left −80 −90 −100 20 100 1k 10k 20k f − Frequency − Hz G015 Figure 17.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com ERROR REPORTING Any fault resulting in device shutdown is signaled by the FAULT pin going low (see Table 1). A sticky version of this pin is available on D1 of register 0X02. Table 1.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 PWM Section The TAS5710 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high power efficiency and high-performance digital audio reproduction.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.
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TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCLK toggles.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 I2C SERIAL CONTROL INTERFACE The TAS5710 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5710 also supports sequential I2C addressing.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 Single-Byte Read As shown in Figure 30, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Dynamic Range Control (DRC) The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/right channels and one DRC for the subwoofer channel. Output Level (dB) The DRC input/output diagram is shown in Figure 32.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 BiQuad Structure All biquads use a 2nd order IIR filter structure as shown below. Each biquad has 3 coefficients on the direct path (b0,b1,b2) and 2 coefficients on feedback path (a1 and a2) as shown in the diagram.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com BANK SWITCHING The TAS5710 uses an approach called bank switching together with automatic sample-rate detection. All processing features that must be changed for different sample rates are stored internally in the TAS5710.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 35. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com APPLICATION INFORMATION Calculation of Output Signal Level of TAS5710 Feedback Power Stage (Gain Is independent of PVCC) The gain of the TAS5710 is the total digital gain of the controller multiplied by the gain of the power stage.
Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5710 PVCC/AVCC RESET HIZ SCL SDA I C 2 MCLK LRCLK SCLK SDIN 2 I S PDN AVDD/DVDD 3V 10 V 7.5 V tVDDH-PVCCL tDV-RH tVDDH-DL tPVCCH-I2C tRH-I2C Trim tPOR Other Config tautodetect DAP Config Stable and Valid Clocks Initialization Exit SD texitSD texitSD tPOR (Reconfigure DAP After Shutdown) tRL-PVCCH Powerdown tDL-VDDH 10 V 7.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com PARAMETER DESCRIPTION MIN MAX UNIT tVDDH-DL Time digital inputs must remain low after AVDD/DVDD goes above 3V 0 µs tDL-VDDH Time digital inputs must be low before AVDD/DVDD goes below 3V 0 µs 100 µs tVDDH-PVCCL Time PVCC/AVCC remains below 7.
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TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Shutdown Sequence Enter: 1. Ensure I2S clocks have been stable and valid for at least 50ms. 2. Write 0x40 to register 0x05. 3. Wait at least 1ms+1.3 × tstop (where tstop is specified by register 0x1A). 4.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 Power Loss Sequence (AD BTL) Use the following sequence to powerdown an AD BTL device and its supplies in case of sudden power loss when time does not permit a controlled shutdown: 1. Assert PDN = 0 and wait at least 2ms then assert HIZ = 0 and wait at least 4µs. 2.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Table 2. Serial Control Interface Register Summary (continued) SUBADDRESS 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 36 REGISTER NAME ch1_bq[0] ch1_bq[1] ch1_bq[2] ch1_bq[3] ch1_bq[4] ch1_bq[5] ch1_bq[6] ch2_bq[0] ch2_bq[1] NO.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 Table 2. Serial Control Interface Register Summary (continued) SUBADDRESS 0x32 0x33 0x34 0x35 0x36 REGISTER NAME ch2_bq[2] ch2_bq[3] ch2_bq[4] ch2_bq[5] ch2_bq[6] 0X37 - 0X39 0x3A DRC1 ae (4) NO.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Table 2.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 Table 2. Serial Control Interface Register Summary (continued) SUBADDRESS 0x5D 0x5E 0x5F REGISTER NAME ch2 BQ[8] ch3 BQ[0] ch3 BQ[1] 0x60–0xF8 0XF9 Update Dev Address Reg 0xFA–0xFF (5) NO.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com CLOCK CONTROL REGISTER (0x00) The clocks and data rates are automatically determined by the TAS5710. The clock control register contains the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 ERROR STATUS REGISTER (0x02) The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com SERIAL DATA INTERFACE REGISTER (0x04) As shown in Table 7, the TAS5710 supports 9 serial data modes. The default is 24-bit, I2S mode, Table 7.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 SOFT MUTE REGISTER (0x06) Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute). Table 9.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com MASTER FINE VOLUME REGISTER (0x0A) This register can be used to provide precision tuning of master volume. If fine master volume is used, output mixers (0x51 and 0x52) should not be used.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 MODULATION LIMIT REGISTER (0x10) Table 13. Modulation Limit Register (0x10) D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT – – – – – 0 0 0 99.2% – – – – – 0 0 1 98.4% – – – – – 0 1 0 97.7% – – – – – 0 1 1 96.9% – – – – – 1 0 0 96.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 OSCILLATOR TRIM REGISTER (0x1B) The TAS5710 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This reduces system cost because an external reference is not required. Currently, TI recommends a reference resistor value of 18.2 kΩ (1%).
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com INPUT MULTIPLEXER REGISTER (0x20) This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal channels. Table 18.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 CHANNEL 4 SOURCE SELECT REGISTER (0x21) This register selects the channel 4 source. Table 19.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Table 20.
TAS5710 www.ti.com............................................................................................................................................................................................... SLOS605 – JANUARY 2009 BANK SWITCH AND EQ CONTROL (0x50) Table 21.
TAS5710 SLOS605 – JANUARY 2009............................................................................................................................................................................................... www.ti.com Table 21. Bank Switching Command (continued) D7 D6 D5 D4 D3 D2 D1 D0 0 1 – – – – – – – EQ OFF (bypass BQ 0-6 of channels 1 and 2) – 0 – – – – – – Reserved – – 0 – – – – – Ignore bank-mapping in bits D31–D8.Use default mapping.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TAS5710PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 TAS5710PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5710PHPR HTQFP PHP 48 1000 367.0 367.0 38.0 TAS5710PHPR HTQFP PHP 48 1000 336.6 336.6 31.
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