Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Audio amplifier 2-channel (stereo) Class D HTQFP 48 (7x7)

TAS5707, TAS5707A

www.ti.com

SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009

20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC

Check for Samples: TAS5707 TAS5707A

FEATURES

• Audio Input/Output

Night-Mode Listening

– 20-W Into an 8-Ω Load From an 18-V Supply – Autobank Switching: Preload Coefficients

for Different Sample Rates. No Need to

– Wide PVDD Range, From 8 V to 26 V

Write New Coefficients to the Part When

– Efficient Class-D Operation Eliminates

Sample Rate Changes.

Need for Heatsinks

– Autodetect: Automatically Detects

– Requires Only 3.3 V and PVDD

Sample-Rate Changes. No Need for

– One Serial Audio Input (Two Audio

External Microprocessor Intervention

Channels)

– Supports 8-kHz to 48-kHz Sample Rate

APPLICATIONS

(LJ/RJ/I

• Television

• Audio/PWM Processing

• iPod™ Dock

– Independent Channel Volume Controls With

• Sound Bar

24 dB to Mute

DESCRIPTION

– Soft Mute (50% Duty Cycle)

– Programmable Dynamic Range Control

The TAS5707 is a 20-W, efficient, digital-audio power

amplifier for driving stereo bridge-tied speakers. One

– 14 Programmable Biquads for Speaker EQ

serial data input allows processing of up to two

and Other Audio Processing Features

discrete audio channels and seamless integration to

– Programmable Coefficients for DRC Filters

most digital audio processors and MPEG decoders.

– DC Blocking Filters

The device accepts a wide range of input data and

data rates. A fully programmable data path routes

• General Features

these channels to the internal speaker drivers.

– Serial Control Interface Operational Without

MCLK The TAS5707 is a slave-only device receiving all

clocks from external sources. The TAS5707 operates

– Factory-Trimmed Internal Oscillator for

with a PWM carrier between a 384-kHz switching rate

Automatic Rate Detection

and 352-KHz switching rate, depending on the input

– Surface Mount, 48-PIN, 7-mm × 7-mm

sample rate. Oversampling combined with a

HTQFP Package

fourth-order noise shaper provides a flat noise floor

and excellent dynamic range from 20 Hz to 20 kHz..

– Thermal and Short-Circuit Protection

• Benefits

The TAS5707A is identical in function to the HTQFP

packaged TAS5707, but has a unique I

C device

– EQ: Speaker Equalization Improves Audio

address. The address of the TAS5707 is 0x36. The

Performance

address of the TAS5707A is 0x3A.

– DRC: Dynamic Range Compression. Can

Be Used As Power Limiter. Enables

Speaker Protection, Easy Listening,

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2iPod is a trademark of Apple Inc.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (58 pages)

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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC Check for Samples: TAS5707 TAS5707A FEATURES 1 • 23 • • • Audio Input/Output – 20-W Into an 8-Ω Load From an 18-V Supply – Wide PVDD Range, From 8 V to 26 V – Efficient Class-D Operation Eliminates Need for Heatsinks – Requires Only 3.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TAS5707, TAS5707A www.ti.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com FAULT Undervoltage Protection FAULT 4 4 Power On Reset Protection and I/O Logic AGND Temp.
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TAS5707, TAS5707A www.ti.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com PIN FUNCTIONS PIN NAME TYPE NO. (1) 5-V TOLERANT TERMINATION DESCRIPTION (2) AGND 30 P Analog ground for power stage AVDD 13 P 3.3-V analog power supply AVSS 9 P Analog 3.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 PIN FUNCTIONS (continued) PIN NAME TYPE 5-V TOLERANT (1) NO. TERMINATION DESCRIPTION (2) SSTIMER 6 AI Controls ramp time of OUT_X to minimize pop. Leave this pin floating for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The capacitor determines the ramp time. STEST 26 DI Factory test pin. Connect directly to DVSS. VR_ANA 12 P Internally regulated 1.8-V analog supply voltage.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com RECOMMENDED OPERATING CONDITIONS (continued) MIN TJ (1) Operating junction temperature range RL (BTL) LO (BTL) (1) NOM 0 Load impedance Output filter: L = 15 μH, C = 680 nF. Output-filter inductance Minimum output inductance under short-circuit condition 6 MAX UNIT 125 °C Ω 8 10 μH Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS PARAMETER fMCLKI tr / tf(MCLK) TEST CONDITIONS MIN MCLK Frequency 2.8224 MCLK duty cycle 40% TYP 50% MAX UNIT 24.576 MHz 60% Rise/fall time for MCLK 5 ns LRCLK allowable drift before LRCLK reset 4 MCLKs External PLL filter capacitor C1 SMD 0603 Y5V 47 nF External PLL filter capacitor C2 SMD 0603 Y5V 4.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com AC Characteristics (BTL) PVDD_X = 18 V, BTL AD mode, FS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter, fPWM = 384 kHz, TA = 25°C (unless otherwise noted). All performance is in accordance with recommended operating conditions, unless otherwise specified.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER MIN CL = 30 pF TYP 1.024 MAX UNIT 12.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com I2C SERIAL CONTROL PORT OPERATION Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN No wait states MAX UNIT 400 kHz fSCL Frequency, SCL tw(H) Pulse duration, SCL high 0.6 μs tw(L) Pulse duration, SCL low 1.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 RESET TIMING (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals. PARAMETER tw(RESET) Pulse duration, RESET active td(I2C_ready) Time to enable I2C MIN TYP MAX UNIT 13.5 ms 100 us RESET tw(RESET) 2 2 I C Active I C Active td(I2C_ready) System Initialization. 2 Enable via I C.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 10 PVDD = 8 V RL = 8 Ω P = 2.5 W 1 0.1 P = 0.5 W P=1W 0.01 0.001 20 100 1k PVDD = 18 V RL = 8 Ω 1 f = 1 kHz 0.1 f = 20 Hz 0.01 f = 10 kHz 0.001 0.01 10k 20k 0.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) OUTPUT POWER vs SUPPLY VOLTAGE EFFICIENCY vs OUTPUT POWER 20 100 RL = 8 Ω 18 90 80 PVDD = 18 V 14 PVDD = 12 V 70 THD+N = 10% Efficiency − % PO − Output Power − W 16 12 10 THD+N = 1% 8 PVDD = 8 V 60 50 40 30 6 20 4 10 2 RL = 8 Ω 0 8 9 10 11 12 13 14 15 16 17 18 0 PVDD − Supply Voltage − V 16 20 24 Figure 13.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) CROSSTALK vs FREQUENCY 0 −10 −20 PO = 0.25 W PVDD = 8 V RL = 8 Ω Crosstalk − dB −30 −40 −50 −60 Right to Left −70 −80 Left to Right −90 −100 20 100 1k 10k 20k f − Frequency − Hz G015 Figure 16.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 DETAILED DESCRIPTION POWER SUPPLY To facilitate system design, the TAS5707 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com Overtemperature Protection The TAS5707 has a two-level temperature-protection system that asserts an active-high warning signal (OTW) when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds 150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and FAULT being asserted low.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and can be enabled and disabled. Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 Left-Justified Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com 2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 21 LSB 17 16 9 8 5 4 13 12 5 4 1 0 9 1 0 1 0 MSB LSB 21 17 16 9 8 5 4 19 18 17 13 12 5 4 1 0 15 14 13 9 1 0 23 22 1 0 20-Bit Mode 19 18 17 16-Bit Mode 15 14 13 8 8 T0092-02 NOTE: All data presented in 2s-complement form with MSB first.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 Right-Justified Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCLK toggles.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com 2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 LSB MSB 23 22 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 20-Bit Mode 16-Bit Mode T0092-03 Figure 24. Right Justified 48-fS Format Figure 25.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 I2C SERIAL CONTROL INTERFACE The TAS5707 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations. This is a slave only device that does not support a multimaster bus environment or wait state insertion.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress. For example, if a write command is received for a biquad subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the data received is discarded.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 Single-Byte Read As shown in Figure 29, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com Dynamic Range Control (DRC) The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/right channels. The DRC input/output diagram is shown in Figure 31. Output Level (dB) K 1:1 Transfer Function O Implemented Transfer Function T Input Level (dB) M0091-02 Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 BANK SWITCHING The TAS5707 uses an approach called bank switching together with automatic sample-rate detection. All processing features that must be changed for different sample rates are stored internally in three banks. The user can program which sample rates map to each bank. By default, bank 1 is used in 32kHz mode, bank 2 is used in 44.1/48 kHz mode, and bank 3 is used for all other rates.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 33. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number.
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2 I C Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A PVDD RESET SCL SDA 0 ns 100 ms 0 ns 0 ns 100 μs 3V 10 ms 8V 6V 13.5 ms Trim 50 ms DAP Config Other Config Stable and Valid Clocks (1) tPLL Exit SD (1) tPLL (2) 1 ms + 1.3 tstart (2) 1 ms + 1.3 tstart Volume and Mute Commands Clock Changes/Errors OK Normal Operation Enter SD 50 ms (2) 1 ms + 1.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com 3V AVDD/DVDD 0 ns PDN 2 ms 0 ns 2 I S 2 ms 0 ns 2 I C 2 ms RESET 2 ms 0 ns 8V PVDD 6V T0420-01 Figure 37. Power Loss Sequence Recommended Command Sequences The DAP has two groups of commands. One set is for configuration and is intended for use only during initialization. The other set has built-in click and pop protection and may be used during normal operation while audio is streaming.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 Normal Operation The following are the only events supported during normal operation: (a) Writes to master/channel volume registers (b) Writes to soft mute register (c) Enter and exit shutdown (sequence defined below) (d) Clock errors and rate changes Note: Events (c) and (d) are not supported for 240ms+1.3*Tstart after trim following AVDD/DVDD powerup ramp (where Tstart is specified by register 0x1A).
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com Table 4. Serial Control Interface Register Summary SUBADDRESS NO. OF BYTES REGISTER NAME CONTENTS INITIALIZATION VALUE A u indicates unused bits.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 NO.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x35 0x36 REGISTER NAME ch2_bq[5] ch2_bq[6] NO.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 CLOCK CONTROL REGISTER (0x00) The clocks and data rates are automatically determined by the TAS5707. The clock control register contains the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The device accepts a 64-fS or 32-fS SCLK rate for all MCLK rates, but accepts a 48-fS SCLK rate for MCLK rates of 192 fS and 384 fS only. Table 5.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com ERROR STATUS REGISTER (0x02) The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors. Error Definitions: • MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing. • SCLK Error: The number of SCLKs per LRCLK is changing. • LRCLK Error: LRCLK frequency is changing.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 SERIAL DATA INTERFACE REGISTER (0x04) As shown in Table 9, the TAS5707 supports 9 serial data modes. The default is 24-bit, I2S mode, Table 9.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com SYSTEM CONTROL REGISTER 2 (0x05) When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are shut down(hard mute). Table 10. System Control Register 2 (0x05) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION (1) 0 – – – – – – – Reserved – 1 – – – – – – Enter all channel shut down (hard mute).
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 VOLUME REGISTERS (0x07, 0x08, 0x09) Step size is 0.5 dB. Master volume – 0x07 (default is mute) Channel-1 volume – 0x08 (default is 0 dB) Channel-2 volume – 0x09 (default is 0 dB) Table 12. Volume Registers (0x07, 0x08, 0x09) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 0 0 0 0 0 0 0 24 dB 0 0 1 1 0 0 0 0 0 dB (default for individual channel volume) 1 1 0 0 1 1 0 1 –78.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com MASTER FINE VOLUME REGISTER (0x0A) This register can be used to provide precision tuning of master volume. Table 13. Master Fine Volume Register (0x0A) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION (1) – – – – – – 0 0 0 dB – – – – – – 0 1 0.125 dB – – – – – – 1 0 0.25 dB – – – – – – 1 1 0.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 MODULATION LIMIT REGISTER (0x10) The modulation limit is the maximum duty cycle of the PWM output waveform. Table 15. Modulation Limit Register (0x10) D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT – – – – – 0 0 0 99.2% – – – – – 0 0 1 98.4% – – – – – 0 1 0 97.7% – – – – – 0 1 1 96.9% – – – – – 1 0 0 96.1% – – – – – 1 0 1 95.3% – – – – – 1 1 0 94.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown.The times are only approximate and vary depending on device activity level and I2S clock stability. Table 17.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 OSCILLATOR TRIM REGISTER (0x1B) The TAS5707 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This reduces system cost because an external reference is not required. Currently, TI recommends a reference resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO. Writing 0X00 to reg 0X1B enables the trim that was programmed at the factory.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com INPUT MULTIPLEXER REGISTER (0x20) This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal channels. Table 20.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 Table 21.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com BANK SWITCH AND EQ CONTROL (0x50) Table 23. Bank Switching Command D31 D30 D29 D28 D27 D26 D25 D24 0 – – – – – – – 32 kHz, does not use bank 3 1 – – – – – – – 32 kHz, uses bank 3 – 0 – – – – – – Reserved (1) – – 0 – – – – – Reserved (1) – – – 0 – – – – 44.1/48 kHz, does not use bank 3 – – – 1 – – – – 44.
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TAS5707, TAS5707A www.ti.com SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 Table 23. Bank Switching Command (continued) D7 D6 D5 D4 D3 D2 D1 D0 0 1 – – – – – – – EQ OFF (bypass BQ 0-6 of channels 1 and 2) – 0 – – – – – – Reserved – – 0 – – – – – Ignore bank-mapping in bits D31–D8.Use default mapping. – – – 0 – – – – L and R can be written independently.
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TAS5707, TAS5707A SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009 www.ti.com Changes from Revision A (November 2008) to Revision B Page • Added TAS5707A device to data sheet ................................................................................................................................ 1 • Changed PVDD maximum voltage to 26 V in Features ....................................................................................................... 1 • Added Applications section ...........
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 21-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TAS5707APHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 TAS5707PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 21-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5707APHPR HTQFP PHP 48 1000 336.6 336.6 31.8 TAS5707PHPR HTQFP PHP 48 1000 336.6 336.6 31.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.