Datasheet

I
2
CSERIALCONTROLINTERFACE
GeneralI
2
COperation
7-BitSlave Address
R/
W
8-BitRegister Address(N)
A
8-BitRegisterDataFor
Address(N)
Start Stop
SDA
SCL
7
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
A
8-BitRegisterDataFor
Address(N)
A A
T0035-01
Single-andMultiple-ByteTransfers
TAS5706A
TAS5706B
SLOS606D–MARCH2009–REVISEDSEPTEMBER2009............................................................................................................................................. www.ti.com
TheTAS5706ADAPhasabidirectionalI
2
CinterfacethatcompatiblewiththeI
2
C(InterIC)busprotocoland
supportsboth100-kHzand400-kHzdatatransferratesforsingleandmultiplebytewriteandreadoperations.
Thisisaslaveonlydevicethatdoesnotsupportamultimasterbusenvironmentorwaitstateinsertion.The
controlinterfaceisusedtoprogramtheregistersofthedeviceandtoreaddevicestatus.
TheDAPsupportsthestandard-modeI
2
Cbusoperation(100kHzmaximum)andthefastI
2
Cbusoperation
(400kHzmaximum).TheDAPperformsallI
2
CoperationswithoutI
2
Cwaitcycles.
TheI
2
Cbusemploystwosignals;SDA(data)andSCL(clock),tocommunicatebetweenintegratedcircuitsina
system.Dataistransferredonthebusseriallyonebitatatime.Theaddressanddatacanbetransferredinbyte
(8-bit)format,withthemostsignificantbit(MSB)transferredfirst.Inaddition,eachbytetransferredonthebusis
acknowledgedbythereceivingdevicewithanacknowledgebit.Eachtransferoperationbeginswiththemaster
devicedrivingastartconditiononthebusandendswiththemasterdevicedrivingastopconditiononthebus.
Thebususestransitionsonthedataterminal(SDA)whiletheclockishightoindicateastartandstop
conditions.Ahigh-to-lowtransitiononSDAindicatesastartandalow-to-hightransitionindicatesastop.Normal
databittransitionsmustoccurwithinthelowtimeoftheclockperiod.TheseconditionsareshowninFigure39.
Themastergeneratesthe7-bitslaveaddressandtheread/write(R/W)bittoopencommunicationwithanother
deviceandthenwaitsforanacknowledgecondition.TheTAS5706AholdsSDAlowduringtheacknowledge
clockperiodtoindicateanacknowledgment.Whenthisoccurs,themastertransmitsthenextbyteofthe
sequence.Eachdeviceisaddressedbyaunique7-bitslaveaddressplusR/Wbit(1byte).Allcompatible
devicessharethesamesignalsviaabidirectionalbususingawired-ANDconnection.Anexternalpullupresistor
mustbeusedfortheSDAandSCLsignalstosetthehighlevelforthebus.
Figure39.TypicalI
2
CSequence
Thereisnolimitonthenumberofbytesthatcanbetransmittedbetweenstartandstopconditions.Whenthelast
wordtransfers,themastergeneratesastopconditiontoreleasethebus.Agenericdatatransfersequenceis
showninFigure39.
The7-bitaddressforTAS5706Ais0011011(0x36).
Theserialcontrolinterfacesupportsbothsingle-byteandmultiple-byteread/writeoperationsforstatusregisters
andthegeneralcontrolregistersassociatedwiththePWM.However,fortheDAPdataprocessingregisters,the
serialcontrolinterfacesupportsonlymultiple-byte(4-byte)read/writeoperations.
Duringmultiple-bytereadoperations,theDAPrespondswithdata,abyteatatime,startingatthesubaddress
assigned,aslongasthemasterdevicecontinuestorespondwithacknowledges.Ifaparticularsubaddressdoes
notcontain32bits,theunusedbitsarereadaslogic0.
Duringmultiple-bytewriteoperations,theDAPcomparesthenumberofbytestransmittedtothenumberofbytes
thatarerequiredforeachspecificsubaddress.Ifawritecommandisreceivedforabiquadsubaddress,theDAP
expectstoreceivefive32-bitwords.Iffewerthanfive32-bitdatawordshavebeenreceivedwhenastop
command(oranotherstartcommand)isreceived,thedatareceivedisdiscarded.Similarly,ifawritecommandis
receivedforamixercoefficient,theDAPexpectstoreceiveone32-bitword.
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TAS5706A is Not Recommended for New Designs