Datasheet

Right-Justified
23
22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
20-BitMode
16-BitMode
15
14
MSB LSB
SCLK
32Clks
RightChannel
2-ChannelRight-Justified(SonyFormat)StereoInput
T0034-03
19 18
1
19 18
1
0
0
0
15
14
15
14
23
22 1
15
14
MSB LSB
19 18
1
19 18
1
0
0
0
15
14
15
14
TAS5706A
TAS5706B
SLOS606D–MARCH2009–REVISEDSEPTEMBER2009............................................................................................................................................. www.ti.com
Right-justified(RJ)timingusesLRCLKtodefinewhenthedatabeingtransmittedisfortheleftchannelandwhen
itisfortherightchannel.LRCLKishighfortheleftchannelandlowfortherightchannel.Abitclockrunningat
32,48,or64×f
S
isusedtoclockinthedata.Thefirstbitofdataappearsonthedata8bit-clockperiods(for
24-bitdata)afterLRCLKtoggles.InRJmodetheLSBofdataisalwaysclockedbythelastbitclockbefore
LRCLKtransitions.ThedataiswrittenMSBfirstandisvalidontherisingedgeofbitclock.TheDAPmasks
unusedleadingdatabitpositions.
Figure36.RightJustified64-f
S
Format
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TAS5706A is Not Recommended for New Designs