Datasheet

TAS5701
www.ti.com SLOS559A –JUNE 2008–REVISED AUGUST 2010
ELECTRICAL CHARACTERISTICS
DC Characteristics
T
A
= 25 °C, PVCC_X = 18 V, DVDD = AVDD = 3.3 V, R
L
= 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage 3.3-V TTL and 5-V tolerant
(1)
I
OH
= –4 mA 2.4 V
V
OL
Low-level output voltage 3.3-V TTL and 5-V tolerant
(1)
I
OL
= 4 mA 0.5 V
LRCLK, SCLK, SDINx, MCLK,
GAIN_x, VREG_EN, V
I
= 0 V, DVDD = 3.6 V ±2
FORMATx, CONFIG_x
I
IL
Low-level input current mA
BKND_ERR, RESET, PDN,
V
I
= 0 V, DVDD = 3.6 V ±50
MUTE
RESET, PDN, MUTE, GAIN_x,
V
I
= 3.6 V, DVDD = 3.6 V ±2
BKND_ERR
VREG_EN, FORMAT_x,
I
IH
High-level input current CONFIG_x, LRCLK, SCLK, V
I
= 3.6 V, DVDD = 3.6 V ±50 mA
SDINx, MCLK
RESET, PDN, MUTE, LRCLK,
V
I
= 5.5 V, DVDD = 3.6 V ±50
SCLK, SDINx, MCLK, GAIN_x
Normal mode, 50% duty cycle 65 80
I
DD
Input digital supply current Supply voltage (DVDD, AVDD) Power down (PDN = low) 8 16 mA
Reset (RESET = low) 23 33
Normal mode, 50% duty cycle 5 10
Gate supply current per
I
GVDD
RESET = 0 2.2 4 mA
GVDD_xx input
PDN = 0 2.2 4
I
PVDD
Input power supply current No load 30 60 mA
I
PVDD
(PDN) Power-down current No load, PDN = 0 1 100 mA
I
PVDD
(RESET) Reset current No load, RESET = 0 1 100 mA
Drain-to-source T
J
= 25°C, includes
140
resistance, LS metallization resistance
r
DS(on)
mΩ
Drain-to-source T
J
= 25°C, includes
140
resistance, HS metallization resistance
I/O Protection
Undervoltage protection
V
uvp
PVDD falling 9.2 V
limit
Undervoltage protection
V
uvp,hyst
PVDD rising 9.6 V
limit
OTE
(2)
Overtemperature error 150 °C
Extra temperature drop
OTE
HYST
(2)
required to recover from 30 °C
error
Overload protection
OLPC f
PWM
= 384 kHz 1.25 ms
counter
Overcurrent limit
I
OC
R
OCP
= 22 kΩ 4.5 A
protection
Overcurrent response
I
OCT
150 ns
time
Resistor tolerance = 5% for
OC programming resistor typical value; the minimum
R
OCP
20 22 kΩ
range resistance should not be less
than 20 kΩ.
Internal pulldown resistor Connected when RESET is
R
PD
at the output of each active to provide bootstrap 3 kΩ
half-bridge capacitor charge.
(1) 5-V tolerant inputs are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2, GAIN_0, and GAIN_1.
(2) Specified by design.
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