Datasheet
AVDD
AVSS
DVDD
MCLK
DVDD
CONFIG_2
DVSSO
DVSS
SDIN1
SDIN2
LRCLK
SCLK
CONFIG_1
MUTE
FORMAT2
OSC_RES
RESET
PDN
GAIN_1
GAIN_0
PLL_FLTM
PLL_FLTP
VR_ANA
VR_DIG
VREG_EN
FORMAT1
TEST1
FORMAT0
BKND_ERR
VALID
SUB_PWM–
SUB_PWM+
GND
GND
VDD
GVDD_AB GVDD_CD
PVDD_A
PVDD_A
PVDD_B
PVDD_B
PVDD_C
PVDD_C
PVDD_D
PVDD_D
PGND_AB
PGND_AB
PGND_CD
PGND_CD
VREG
OC_ADJ
FAULT
OUT_A
OUT_A
OUT_B
OUT_B
OUT_C
OUT_C
OUT_D
OUT_D
BST_A
BST_B
BST_C
BST_D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 19 20
21 22
23
24
25 26
27
28 29
30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
4950515253
54
55
56
57
58596061626364
P0071-03
PAP Package
(TopView)
TAS5701
www.ti.com
SLOS559A –JUNE 2008–REVISED AUGUST 2010
64-PIN, HTQFP PACKAGE (TOP VIEW)
PIN FUNCTIONS
PIN
5-V TERMINATION
I/O
(1)
DESCRIPTION
TOLERANT
(2) (3)
NAME NO.
AVDD 10 P 3.3-V Analog power supply
AVSS 11 P Analog 3.3-V supply ground
BKND_ERR 37 DI Pullup Active low. A back-end error sequence is initiated by applying a logic
low to this pin. Connect to an external power stage. If no external
power stage is used, connect directly to DVDD.
BST_A 4 P High-side bootstrap supply for half-bridge A
BST_B 57 P High-side bootstrap supply for half-bridge B
BST_C 56 P High-side bootstrap supply for half-bridge C
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are 20-mA weak pullups and all pulldowns are 20-mA weak pulldowns. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 50 mA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 50 mA while maintaining a logic-1 drive level.
(3) If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing
parallel resonance circuits that have been observed when paralleling capacitors of different values.
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