Datasheet

LRCK
MSB LSB
1/f
S
(= 32 f
S
, 48 f
S,
or 64 f
S
)
18-Bit Right-Justified, SCLK = 48 f
S
or 64 f
S
MSB LSB
20-Bit Right-Justified, SCLK = 48 f
S
or 64 f
S
LSB
16-Bit Right-Justified, SCLK = 48 f
S
or 64 f
S
16-Bit Right-Justified, SCLK = 32 f
S
LSB
L-Channel R-Channel
SCLK
DATA 2 1 0
2 1 0
2 1 0 2 1 0
2 1 0
DATA
DATA
DATA
17 16 15 2 1 0
2 1 0 19 18 17 2 1 0
MSB LSB
MSB LSB
LSB
MSB LSB
15 14 13 2 1 0
2 1 0
17 16 15 2 1 0
19 18 17 2 1 0
MSB
15 14 13
MSB
15 14 13
MSB
15 14 13
24-Bit Right-Justified, SCLK = 48 f
S
LSB
DATA 2 1 0 2 1 0
MSB LSB
23 22 21 2 1 0
MSB
23 22 21
LSB
24-Bit Right-Justified, SCLK = 64 f
S
2 1 0 2 1 0DATA
LSB
2 1 0
MSB
23 22 21
MSB
23 22 21
TAS5701
www.ti.com SLOS559A –JUNE 2008–REVISED AUGUST 2010
Figure 20. Right-Justified Format
Format Control
The digital data input format is selected via three external terminals (FORMAT0, FORMAT1, and FORMAT2).
Table 1 lists the corresponding data format for SDIN1 and SDIN2. LRCLK and SCLK are shared clocks for
SDIN1 and SDIN2. Changes to the FORMATx terminals are latched in immediately on a rising edge of RESET.
Changes to the FORMATx terminals while RESET is high are not allowed.
Table 1. Format Control
SERIAL DIGITAL DATA
FORMAT2 FORMAT1 FORMAT0
FORMAT
0 0 0 16-Bit right-justifed
0 0 1 18-Bit right-justified
0 1 0 20-Bit right-justified
0 1 1 24-Bit right-justified
1 0 0 16-, 24-Bit I
2
S
1 0 1 16-, 24-Bit left-justified
1 1 0 Reserved. Setting is not allowed.
1 1 1 Reserved. Setting is not allowed.
Gain Control
The gain of the DAP is selected via two external gain pins (GAIN_0 and GAIN_1). Table 2 lists the corresponding
channel gain (for ALL channels) for GAIN_0 and GAIN_1 settings. Individual channel gain is not possible.
Changes to the GAIN_x terminals are latched in immediately on a rising edge of RESET. Changes to the
GAIN_x terminals while RESET is high are not allowed.
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