Datasheet

1/f
S
(= 32 f
S
, 48 f
S
or 64 f
S
)
L-Channel R-ChannelLRCK
SCLK
DATA
N−1 N−2 N−3 N−1 N−2
MSB
0
LSB
1
2 0
MSB
N–2N–1
LSB
12
N–3
1/f
S
(= 32 f
S
, 48 f
S,
or 64 f
S
)
L-Channel R-Channel
LRCK
SLCK
DATA
N−1 N−2 N−3 0 N−1 N−2 N−3 012
MSB LSB LSBMSB
12
N–1
N–2
TAS5701
SLOS559A –JUNE 2008–REVISED AUGUST 2010 www.ti.com
Figure 18. I
2
S Format
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × f
s
is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
Figure 19. Left-Justified Format
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × f
s
is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks
unused leading data bit positions.
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