Datasheet

TAS5631
www.ti.com SLES221C –JULY 2009–REVISED APRIL 2010
MODE SELECTION PINS
MODE PINS
OUTPUT
PWM INPUT
(1)
DESCRIPTION
CONFIGURATION
M3 M2 M1
0 0 0 2N 2 × BTL AD mode
0 0 1 — — Reserved
0 1 0 2N 2 × BTL BD mode
0 1 1 1N 1 × BTL +2 × SE AD mode
1 0 0 1N 4 × SE AD mode
INPUT_C
(2)
INPUT_D
(2)
2N
1 0 1 1 × PBTL 0 0 AD mode
1N
1 0 BD mode
1 1 0
Reserved
1 1 1
(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
(2) INPUT_C and INPUT_D are used to select between a subset of AD and BD mode operations in PBTL mode.
PACKAGE HEAT DISSIPATION RATINGS
(1)
PARAMETER TAS5631PHD TAS5631DKD
R
qJC
(°C/W) – 2 BTL or 4 SE channels 2.63 14
R
qJC
(°C/W) – 1 BTL or 2 SE channel(s) 4.13 2.04
R
qJC
(°C/W) – 1 SE channel 6.45 3.45
Pad area
(2)
64 mm
2
80 mm
2
(1) R
qJC
is junction-to-case; R
qCH
is case-to-heatsink.
(2) R
qCH
is an important consideration. Assume a 2-mil (0.051-mm) thickness of thermal grease with a thermal conductivity of 2.5 W/mK
between the pad area and the heat sink and both channels active. The R
qCH
with this condition is 1.1°C/W for the PHD package and
0.44°C/W for the DKD package.
Table 1. ORDERING INFORMATION
(1)
T
A
PACKAGE DESCRIPTION
0°C–70°C TAS5631PHD 64-pin HTQFP
0°C–70°C TAS5631DKD 44-pin PSOP3
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TAS5631
Not Recommended For New Designs