Datasheet

2-CHANNEL
H-BRIDGE
BTL MODE
Output
H-Bridge 2
PVDD_A, B, C, D GND_A, B, C, D
Hardwire
Over-
Current
Limit
8
GND
VDD VREG
AGND
OC_ADJ
PVDD
Power Supply
Decoupling
GVDD, VDD,
and VREG
Power Supply
Decoupling
SYSTEM
Power
Supplies
PVDD
GVDD (12V)/VDD (12V)
GND
50V
12V
GND
VAC
Bootstrap
Caps
BST_C
BST_D
2
nd
Order
L-C Output
Filter for
each
H-Bridge
OUT_C
OUT_D
GVDD_A, B, C, D
Bootstrap
Caps
BST_A
BST_B
INPUT_A
2
nd
Order
L-C Output
Filter for
each
H-Bridge
OUT_A
OUT_B
8 4
Output
H-Bridge 1
Input
H-Bridge 1
INPUT_B
M2
M1
M3
Hardwire
Mode
Control
Input
H-Bridge 2
INPUT_C
INPUT_D
VI_CM
C_STARTUP
PSU_REF
Caps for
External
Filtering
and
Startup/Stop
/OTW1, /OTW2, /OTW
/CLIP
System
microcontroller
READY
/SD
PWM_A
PWM_B
PWM_C
PWM_D
2
2
2
2
(2)
TAS5518/
TAS5508/
TAS5086
I2C
Left-
Channel
Output
Right-
Channel
Output
VALID
RESET
TEST
AMP RESET
*NOTE1
TAS5631B
SLES263C –NOVEMBER 2010–REVISED SEPTEMBER 2012 www.ti.com
PIN FUNCTIONS (continued)
PIN
Function
(1)
DESCRIPTION
NAME PHD NO. DKD NO.
VREG 9 11 P Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.
TYPICAL SYSTEM BLOCK DIAGRAM
(1) Logic AND is inside or outside the microcontroller.
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