Datasheet

TAS5631B
SLES263C –NOVEMBER 2010–REVISED SEPTEMBER 2012 www.ti.com
ELECTRICAL CHARACTERISTICS
PVDD_X = 50V, GVDD_X = 12 V, VDD = 12V, T
C
(case temperature) = 75°C, f
S
= 384 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG VDD = 12 V 3 3.3 3.6 V
node, VREG
VI_CM Analog comparator reference node, VI_CM 1.5 1.75 1.9 V
Operating, 50% duty cycle 22.5
I
VDD
VDD supply current mA
Idle, reset mode 22.5
50% duty cycle 12.5
I
GVDD_x
Gate-supply current per half-bridge mA
Reset mode 1.5
50% duty cycle without output filter or
19.5 mA
load
I
PVDD_x
Half-bridge idle current
Reset mode, no switching 750 μA
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS) T
J
= 25°C, excludes metallization 60 100 mΩ
resistance,
R
DS(on)
Drain-to-source resistance, high side (HS) 60 100 mΩ
GVDD = 12 V
I/O PROTECTION
V
uvp,G
Undervoltage protection limit, GVDD_X, VDD 9.5 V
V
uvp,hyst
(1)
0.6 V
OTW1
(1)
Overtemperature warning 1 95 100 105 °C
OTW2
(1)
Overtemperature warning 2 115 125 135 °C
Temperature drop needed below OTW temperature for OTW to be inactive after OTW
OTW
hyst
(1)
25 °C
event
Overtemperature error 145 155 165 °C
OTE
(1)
OTE-OTW differential 30 °C
OTE
HYST
(1)
A reset must occur for SD to be released following an OTE event 25 °C
OLPC Overload protection counter f
PWM
= 384 kHz 2.6 ms
Nominal peak current in 1-Ω load,
64-pin QFP package (PHD) 15 A
R
OCP
= 22 kΩ
Overcurrent limit
Nominal peak current in 1-Ω load,
I
OC
44-pin PSOP3 package (DKD) 15 A
R
OCP
= 24 kΩ
Nominal peak current in 1-Ω load,
Overcurrent latched 15 A
R
OCP
= 47 kΩ
Connected when RESET is active to
Internal pulldown resistor at output of each
I
PD
provide bootstrap charge. Not used in SE 3 mA
half-bridge
mode.
STATIC DIGITAL SPECIFICATIONS
V
IH
High-level input voltage 1.9 V
INPUT_X, M1, M2, M3, RESET
V
IL
Low-level input voltage 1.45 V
I
lkg
Input leakage current 100 μA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW, OTW1,
R
INT_PU
20 26 33 kΩ
OTW2, CLIP, READY, SD to VREG
Internal pullup resistor 3 3.3 3.6
V
OH
High-level output voltage V
External pullup of 4.7 kΩ to 5 V 4.5 5
V
OL
Low-level output voltage I
O
= 4 mA 200 500 mV
Device fanout OTW, OTW1, OTW2, SD,
FANOUT No external pullup 30 devices
CLIP, READY
(1) Specified by design
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