Datasheet

TAS5630B
SLES217C –NOVEMBER 2010–REVISED SEPTEMBER 2012 www.ti.com
AUDIO SPECIFICATION (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V,
GVDD_X = 12 V, R
L
= 3 Ω, f
S
= 400 kHz, R
OC
= 22 kΩ, T
C
= 75°C; output filter: L
DEM
= 7 μH, C
DEM
= 1.5 μF,
MODE = 101-10, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R
L
= 3 Ω, 10% THD+N, clipped output signal 400
R
L
= 4 Ω, 10% THD+N, clipped output signal 300
P
O
Power output per channel W
R
L
= 3 Ω, 1% THD+N, unclipped output signal 310
R
L
= 4 Ω, 1% THD+N, unclipped output signal 230
THD+N Total harmonic distortion + noise 1 W 0.05%
V
n
Output integrated noise A-weighted 260 μV
SNR Signal to noise ratio
(1)
A-weighted 100 dB
DNR Dynamic range A-weighted 100 dB
P
idle
Power dissipation due to idle losses (IPVDD_X) P
O
= 0, four channels switching
(2)
2.7 W
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, T
C
(Case temperature) = 75°C, f
S
= 400 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG VDD = 12 V 3 3.3 3.6 V
node, VREG
VI_CM Analog comparator reference node, VI_CM 1.75 2 2.15 V
Operating, 50% duty cycle 22.5
I
VDD
VDD supply current mA
Idle, reset mode 22.5
50% duty cycle 12.5
I
GVDD_X
GVDD_x gate-supply current per half-bridge mA
Reset mode 1.5
50% duty cycle with recommended output
13.3 mA
filter
I
PVDD_X
Half-bridge supply current
Reset mode, No switching 870 μA
ANALOG INPUTS
R
IN
Input resistance READY = HIGH 33 kΩ
Maximum input voltage with symmetrical
V
IN
5 V
PP
output swing
I
IN
Maximum input current 342 μA
G Voltage gain (V
OUT
/V
IN
) 23 dB
OSCILLATOR
Nominal, master mode 3.85 4 4.15
f
OSC_IO+
AM1, master mode F
PWM
× 10 3.15 3.33 3.5 MHz
AM2, master mode 2.6 3 3.35
V
IH
High level input voltage 1.86 V
V
IL
Low level input voltage 1.45 V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS) 60 100 mΩ
T
J
= 25°C, excludes metallization
R
DS(on)
resistance, GVDD = 12 V
Drain-to-source resistance, high side (HS) 60 100 mΩ
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