Datasheet

TAS5624A
www.ti.com SLAS844 –MAY 2012
RECOMMENDED OPERATING CONDITIONS
MIN TYP MAX UNIT
PVDD_X Full-bridge supply DC supply voltage 12 36 38 V
Supply for logic regulators and gate-drive
GVDD_X DC supply voltage 10.8 12 13.2 V
circuitry
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
BTL 2.5 4.0
Output filter: L = 10 uH, 1 µF.
R
L
Load impedance SE Output AD modulation, 1.5 3.0 Ω
switching frequency > 350 kHz.
PBTL 1.5 2.0
Minimum inductance at overcurrent limit,
L
OUTPUT
Output filter inductance including inductor tolerance, temperature 5 μH
and possible inductor saturation
F
PWM
PWM frame rate 352 384 500 kHz
C
PVDD
PVDD close decoupling capacitors 0.44 1 μF
BTL and PBTL configuration 100 nF
C_START Startup ramp capacitor
SE and 1xBTL+2xSE configuration 1 μF
R
OC
Over-current programming resistor Resistor tolerance = 5% 24 33 kΩ
R
OC_LATCHED
Over-current programming resistor Resistor tolerance = 5% 47 62 68 kΩ
T
J
Junction temperature 0 125 °C
MODE SELECTION PINS
MODE PINS
PWM Input Output Configuration Input A Input B Input C Input D MODE
M3 M2 M1
0 0 0 2N + 1 2 x BTL PWMa PWMb PWMc PWMd AD Mode
0 0 1 1N + 1
(1)
2 x BTL PWMa Unused PWMc Unused AD Mode
0 1 0 2N + 1 2 x BTL PWMa PWMb PWMc PWMd BD Mode
0 1 1 1N + 1
(1)
1 x BTL + 2 x SE PWMa Unused PWMc PWMd AD Mode
1 0 0 2N + 1 1 x PBTL PWMa PWMb 0 0 AD Mode
1 0 0 1N + 1
(1)
1 x PBTL PWMa Unused 0 1 AD Mode
1 0 0 2N + 1 1 x PBTL PWMa PWMb 1 0 BD Mode
1 0 1 1N + 1 4 x SE
(2)
PWMa PWMb PWMc PWMd AD Mode
(1) Using 1N interface in BTL and PBTL mode results in increased DC offset on the output terminals.
(2) The 4xSE mode can be used as 1xBTL + 2xSE configuration by feeding a 2N PWM signal to either INPUT_AB or INPUT_CD for
improved DC offset accuracy
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