Datasheet

TAS5624A
www.ti.com SLAS844 –MAY 2012
UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5624A fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and FAULT being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.
ERROR REPORTING
Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system micro controller and responding to an overtemperature
warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device
shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on FAULT, CLIP, and OTW
outputs. See Electrical Characteristics table for actual values.
The FAULT, OTW, pins are active-low, open-drain outputs. Their function is for protection-mode signaling to a
PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Likewise, OTW goes low when
the device junction temperature exceeds 125°C (see the following table).
Table 4. Error Reporting
FAULT OTW DESCRIPTION
0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
0 1 Overload (OLP) or undervoltage (UVP)
1 0 Junction temperature higher than 125°C (overtemperature warning)
1 1 Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
FAULT HANDLING
If a fault situation occurs while in operation, the device will act accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and will cause all PWM activity of the device to be shut down,
and will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires
resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the OTW signal is cleared (high). A channel fault will result in shutdown of the PWM activity of
the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults
being present. TI recommends monitoring the OTW signal using the system micro controller and responding to
an over temperature warning signal by, e.g., turning down the volume to prevent further heating of the device
resulting in device shutdown (OTE).
Table 5. Fault Handling
Fault/Event Global or
Reporting Latched/Self
Fault/Event Action needed to Clear Output FETs
Method Clearing
Description Channel
PVDD_X UVP
VDD UVP
Increase affected supply
Voltage Fault Global FAULT Pin Self Clearing Hi-Z
voltage
GVDD_X UVP
AVDD UVP
Power On
POR (DVDD UVP) Global FAULT Pin Self Clearing Allow DVDD to rise H-Z
Reset
Allow BST cap to recharge
Channel (half
BST UVP Voltage Fault None Self Clearing HighSide Off
bridge)
(lowside on, VDD 12V)
Thermal Cool below lower OTW
OTW Global OTW Pin Self Clearing Normal operation
Warning threshold
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