Datasheet

TAS5611
SLAS681A –DECEMBER 2009–REVISED APRIL 2010 www.ti.com
ELECTRICAL CHARACTERISTICS
PVDD_X = 32.5V, GVDD_X = 12 V, VDD = 12 V, T
C
(Case temperature) = 75°C, f
S
= 400 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
VREG VDD = 12 V 3 3.3 3.6 V
node, VREG
VI_CM Analog comparator reference node, VI_CM 1.5 1.75 1.9 V
Operating, 50% duty cycle 20
I
VDD
VDD supply current mA
Idle, reset mode 20
50% duty cycle 10
I
GVDD_X
GVDD_x gate-supply current per half-bridge mA
Reset mode 1.5
50% duty cycle with recommended output
10 mA
filter
I
PVDD_X
Half-bridge supply current
Reset mode, No switching 540 mA
ANALOG INPUTS
R
IN
Input resistance READY = HIGH 33 kΩ
V
IN
Maximum input voltage swing 7 V
I
IN
Maximum input current 1 mA
G Voltage Gain (V
OUT
/V
IN
) 21 dB
OSCILLATOR
Nominal, Master Mode 3.5 4 4.5
f
OSC_IO+
AM1, Master Mode F
PWM
× 10 3.0 3.4 3.8 MHz
AM2, Master Mode 2.6 3 3.35
V
IH
High level input voltage 1.86 V
V
IL
Low level input voltage 1.45 V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS) 60 100 mΩ
T
J
= 25°C, excludes metallization
R
DS(on)
resistance, GVDD = 12 V
Drain-to-source resistance, high side (HS) 60 100 mΩ
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