Datasheet

TAS5548
www.ti.com SLES270 –NOVEMBER 2012
11.32 ASRC Registers (0xC3-C5)
Table 11-39. ASRC Status 0xC3 (Read Only)
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 ASRC #1 is down sampling
1 ASRC #1 is up sampling
0 ASRC #2 is down sampling
1 ASRC #2 is up sampling
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 ASRC #1 clocks are valid
1 Error in ASRC #1 clocks
0 ASRC #2 clocks are valid
1 Error in ASRC #2 clocks
0 ASRC #1 is unlocked
1 ASRC #1 is locked
0 ASRC #2 is unlocked
1 ASRC #1 is locked
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 ASRC #1 is unmuted
1 ASRC #1 is muted
0 ASRC #2 is unmuted
1 ASRC #2 is muted
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 RESERVED
1 RESERVED
0 RESERVED
1 RESERVED
Table 11-40. ASRC Control (0xC4)
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 ASRCs in independent mode (clock error on one will not affect
the other)
1 ASRCs in coupled mode (clock error on one will trigger muting of
both ASRCs)
0 ASRC2 uses LRCK and SCK
1 ASRC2 uses LRCK2 and SCK2
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 Normal (32-sample) FIFO latency for ASRC1
1 Low (16-sample) FIFO latency for ASRC1
0 Normal (32-sample) FIFO latency for ASRC2
1 Low (16-sample) FIFO latency for ASRC2
0 Do not dither ASRC output
1 Dither ASRC output before truncation back to 24-bit
0 ASRC unlock will not cause ASRC clock error
1 ASRC unlock will cause ASRC clock error
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 ASRC1 is enabled
1 ASRC1 is bypassed
Copyright © 2012, Texas Instruments Incorporated Serial-Control Interface Register Definitions 99
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