Datasheet

TAS5548
www.ti.com SLES270 –NOVEMBER 2012
11.28 DRC2 Data Registers (0x9D–0xA1)
DRC2 applies to channel 8.
Table 11-32. DRC2 Data Register Format
I
2
C
TOTAL
REGISTER NAME DESCRIPTION OF CONTENTS DEFAULT STATE DATA DECIMAL
SUBADDRES
BYTES
S
Channel 8 DRC2 energy u[31:28], E[27:24], E[23:16], E[15:8], E[7:0] 0000 883F mS
0x9D 8
Channel 8 DRC2 (1 – u[31:28], 1–E[27:24], 1–E[23:16], 1–E[15:8], 1–E[7:0] 007F 77C0
energy)
Channel 8 DRC2 T1[31:24], T1[23:16], T1[15:8], T1[7:0] 0B20 E2B2 dB
threshold lower 32 bits
(T1)
0x9E 8
Channel 8 DRC2 T2[31:24], T2[23:16], T2[15:8], T2[7:0] 06F9 DE58 dB
threshold lower 32 bits
(T2)
Channel 8 DRC2 slope u[31:28], k0[27:24], k0[23:16], k0[15:8], k0[7:0] 0040 0000 ratio
(k0)
Channel 8 DRC2 slope u[31:28], k1[27:24], k1[23:16], k1[15:8], k1[7:0] 0FC0 0000 ratio
0x9F 12
(k1)
Channel 8 DRC2 slope u[31:28], k2[27:24], k2[23:16], k2[15:8], k2[7:0] 0F90 0000 ratio
(k2)
Channel 8 DRC2 offset 1 O1[31:24], O1[23:16], O1[15:8], O1[7:0] FF82 3098 dB
lower 32 bits (O1)
0xA0 8
Channel 8 DRC2 offset 2 O2[31:24], O2[23:16], O2[15:8], O2[7:0] 0195 B2C0 dB
lower 32 bits (O2)
Channel 8 DRC2 attack u[31:28], A[27:24], A[23:16], A[15:8], A[7:0] 0000 883F mS
Channel 8 DRC2 (1 – u[31:28], 1–A[27:24], 1–A[23:16], 1–A[15:8], 1–A[7:0] 007F 77C0
attack)
0xA1 16
Channel 8 DRC2 decay u[31:28], D[27:24], D[23:16], D[15:8], D[7:0] 0000 0056 mS
Channel 8 DRC2 (1 – u[31:28], 1–D[27:24], 1–D[23:16], 1–D[15:8], 003F FFA8
decay) 1–D[7:0]
11.29 DRC Bypass Registers (0xA2–0xA9)
DRC bypass/inline for channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xA2, 0xA3, 0xA4,
0xA5, 0xA6, 0xA7, 0xA8, and 0xA9, respectively. Eight bytes are written for each channel. Each gain
coefficient is in 28-bit (5.23) format, so 0x0080 0000 is a gain of 1. Each gain coefficient is written as a 32-
bit word with the upper 4 bits not used.
To enable DRC for a given channel (with unity gain), bypass = 0x0000 0000 and inline = 0x0080 0000.
To disable DRC for a given channel, bypass = 0x0080 0000 and inline = 0x0000 0000.
Table 11-33. DRC Bypass Register Format
TOTAL
REGISTER NAME CONTENTS DEFAULT VALUE
BYTES
Channel bass DRC bypass u[31:28], bypass[27:24], bypass[23:16], bypass[15:8], bypass[7:0] 0x00, 0x80, 0x00, 0x00
8
Channel DRC inline u[31:28], inline[27:24], inline[23:16], inline[15:8], inline[7:0] 0x00, 0x00, 0x00, 0x00
11.30 Output Select and Mix Registers 8x2 (0x–0xAF)
The pass-through output mixer setting is:
• DAP channel 1 is mapped though the 8×2 crossbar mixer (0xAA) to PWM channel 1
• DAP channel 2 is mapped though the 8×2 crossbar mixer (0xAB) to PWM channel 2
• DAP channel 3 is mapped though the 8×2 crossbar mixer (0xAC) to PWM channel 3
• DAP channel 4 is mapped though the 8×2 crossbar mixer (0xAD) to PWM channel 4
• DAP channel 5 is mapped though the 8×2 crossbar mixer (0xAE) to PWM channel 5
Copyright © 2012, Texas Instruments Incorporated Serial-Control Interface Register Definitions 95
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