Datasheet

TAS5548

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SLES270 –NOVEMBER 2012

Table 11-21. PWM Registers Format

D6/D2 D5/D1 D4/D0 FUNCTION

0 0 0 Select channel 1

0 0 1 Select channel 2

0 1 0 Select channel 3

0 1 1 Select channel 4

1 0 0 Select channel 5

1 0 1 Select channel 6

1 1 0 Select channel 7

1 1 1 Select channel 8

11.19 BD mode and Ternary - 8 Interchannel Channel Delay (0x38 to 0x3F)

Interchannel delay is used to distribute the switching current of each channel, to ease the peak power

draw on the PSU. It's also used to control the intermodulation between the channels, therefore improving

THD in some cases.

DCLK is the oversampling clock of the PWM.

DCLK on the TAS5548 will be constant, unless some AM avoidance modes are used.

Each channel can have its channel delay set between -128 to +124. (4 DCLK steps value (-32 to +31 over

5 bits))

Channels 0, 1, 2, 3, 4, 5, 6, 7 are mapped into (0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F) with

bits D[7:2] used to program individual DCLK delay. Bit D[1:0] are reserved in each register.

Table 11-22. Interchannel Delay Register Format (0x38B to 0x3F)

D7 D6 D5 D4 D3 D2 FUNCTION

0 0 0 0 0 0 Minimum absolute delay, 0 DCLK cycles

0 1 1 1 1 1 Maximum positive delay, 31(×4) DCLK cycles

1 0 0 0 0 0 Maximum Negative delay, –32(×4) DCLK cycles

1 0 0 0 0 0 Default Value for channel 0 = -128 DCLK's (–32*4)

0 0 0 0 0 0 Default Value for channel 1 0

1 1 0 0 0 0 Default Value for channel 2 = -64DCLK's (–16*4)

0 1 0 0 0 0 Default Value for channel 3 = 64 DCLK's (16*4)

1 0 1 0 0 0 Default Value for channel 4 = -96 DCLK's (–24*4)

0 0 1 0 0 0 Default Value for channel 5 = 32 DCLK's (8*4)

1 1 1 0 0 0 Default Value for channel 6 = -32 DCLK's (–8*4)

0 1 1 0 0 0 Default Value for channel 7 = 96 DCLK's (24*4)

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