Datasheet

TAS5548
www.ti.com SLES270 –NOVEMBER 2012
11.12 Modulation Index Limit Register (0x16, 0x17, 0x18, 0x19)
Note that some power stages require a lower modulation limit than the default of 93.7%. Contact Texas
Instruments for more details about the requirements for a particular power stage.
Table 11-12. Modulation Limit Register Format
Di LIMIT MIN WIDTH MODULATION
Di+3 Di+2 Di+1
(i=0 or 4) [DCLKs] [DCLKs] INDEX
0 0 0 0 1 2 99.21%
0 0 0 1 2 4 98.43%
0 0 1 0 3 6 97.64%
0 0 1 1 4 8 96.85%
0 1 0 0 5 10 96.06%
0 1 0 1 6 12 95.28%
0 1 1 0 7 14 94.49%
0 1 1 1 8 16 93.70%
1 0 0 0 9 18 92.91%
1 0 0 1 10 20 92.13%
1 0 1 0 11 22 91.34%
1 0 1 1 12 24 90.55%
1 1 0 0 13 26 89.76%
1 1 0 1 14 28 88.98%
1 1 1 0 15 30 88.19%
1 1 1 1 16 32 87.40%
There are 512 DCLK Cycles per PWM frame.
Table 11-13. Modulation Index Limit Register
Register Address D7 D6 D5 D4 D3 D2 D1 D0
x16 Modulation limit for channel 2 Modulation limit for channel 1
x17 Modulation limit for channel 4 Modulation limit for channel 3
x18 Modulation limit for channel 6 Modulation limit for channel 5
x19 Modulation limit for channel 8 Modulation limit for channel 7
Copyright © 2012, Texas Instruments Incorporated Serial-Control Interface Register Definitions 83
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