Datasheet

TAS5548
SLES270 –NOVEMBER 2012 www.ti.com
2.4 TAS5548 Functional Description
Figure 1-1 shows the TAS5548 functional structure. The following sections describe the TAS5548
functional blocks:
• Power Supply
• Clock, PLL, and Serial Data Interface
• Serial Control Interface
• Device Control
• Digital Audio Processor
• PWM Section
• 8 Channel ASRC
2.4.1 Power Supply
The power-supply section contains 1.8 V supply regulators that provide analog and digital regulated power
for various sections of the TAS5548. The analog supply supports the analog PLL, whereas digital supplies
support the digital PLL, the digital audio processor (DAP), the pulse-width modulator (PWM), and the
output control.
2.4.2 Clock, PLL, and Serial Data Interface
In the TAS5548, the internal master clock is derived from the XTAL and the internal sampling rate will
always be 96 kHz (double speed mode) or 192 kHz (quad speed mode).
There is a fifth (I2S input) SAP input that will not go through the ASRC. Due to this, this fifth SAP input will
be always slave to internal master clock.
Due to the limitation in the ASRC block, in quad speed mode the number of supported channels will be
halved, which happens when the ASRC is set into a certain mode. In this mode, only one serial audio
input (two channels) will be processed per ASRC module and its output will be copied to the other two
channels at the ASRC output.
The TAS5548 uses the external crystal to provide a time base for:
• Continuous data and clock error detection and management
• Automatic data-rate detection and configuration
• Automatic MCLK-rate detection and configuration (automatic bank switching)
• Supporting I
2
C operation/communication while MCLK is absent
The TAS5548 automatically handles clock errors, data-rate changes, and master-clock frequency
changes without requiring intervention from an external system controller. This feature significantly
reduces system complexity and design.
2.4.3 Serial Audio Interface
The TAS5548 has five PCM serial data interfaces to permit eight channels of digital data to be received
through the SDIN1-1, SDIN1-2, SDIN2-1, SDIN2-2 and SDIN5 inputs. The device also has one serial
audio output. The serial audio data is in MSB-first, 2s-complement format.
The serial data input interface can be configured in right-justified, I
2
S, left-justified or TDM modes. The
serial data interface format is specified using the I
2
C data-interface control register. The supported formats
and word lengths are shown in Table 2-1.
Table 2-1. Serial Data Formats
RECEIVE SERIAL DATA FORMAT WORD LENGTH
Right-justified 16
8 Description Copyright © 2012, Texas Instruments Incorporated
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